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| * Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-141-2/+9
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| * \ Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-12-051-2/+4
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Immediate merge for the conflicting introduction of HAS_COHERENT_RINGS. Conflicts: drivers/gpu/drm/i915/i915_dma.c include/drm/i915_drm.h
| * | | agp/intel: Remove duplicate constChris Wilson2010-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | drivers/char/agp/intel-gtt.c:340:48: warning: duplicate const Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: export api for drm/i915Daniel Vetter2010-11-231-52/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just some minor shuffling to get rid of any agp traces in the exported functions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp: kill agp_rebind_memoryDaniel Vetter2010-11-231-20/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its only user, intel-gtt.c is now gone. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915: restore gtt on resume in the drm instead of in intel-gtt.koDaniel Vetter2010-11-231-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This still uses the agp functions to actually reinstate the mappings (with a gross hack to make agp cooperate), but it wires everything up correctly for the switchover. The call to agp_rebind_memory can be dropped because all non-kms drivers do all their rebinding on EnterVT. v2: Be more paranoid and flush the chipset cache after restoring gtt mappings. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp: kill agp_flush_chipset and corresponding ioctlDaniel Vetter2010-11-236-24/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intel drm calls the chipset functions now directly. Userspace never called the corresponding ioctl, hence it can be killed, too. Cc: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915/gtt: call chipset flush directlyDaniel Vetter2010-11-231-0/+7
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | drm/i915|intel-gtt: consolidate intel-gtt.h headersDaniel Vetter2010-11-231-5/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and a few other defines. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: fold i81x-only dcache support into the generic driverDaniel Vetter2010-11-231-89/+61Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now the intel-gtt.c rewrite is complete! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: switch i81x to the common initialization helpersDaniel Vetter2010-11-231-127/+71Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Still a separate agp_bridge_driver because of the i81x-only dedicated vram support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: switch i81x to the write_entry helpersDaniel Vetter2010-11-231-92/+60Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialization is still done with the old code with a few added things sprinkled in to make the intel_fake_agp helper functions work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: kill unneeded sandybridge memory typesDaniel Vetter2010-11-231-6/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Used for the now dead agp type_to_mask stuff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | intel-gtt: drop dcache support for i830 and laterDaniel Vetter2010-11-231-7/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i830_check_flags already disallows it, so no need to implement it in the write_entry function. Seems to be a remnant from i810 support. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp/intel: Remove confusion of stolen entries not stolen memoryChris Wilson2010-11-231-33/+7Star
| | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | agp/intel: Remove the artificial cap on stolen sizeChris Wilson2010-11-231-13/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the stolen memory does not also steal entries from the GTT, we can use all the memory the BIOS set aside for the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-221-1/+0Star
| |\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_gem.c
| * \ \ \ Merge branch 'drm-intel-fixes' into drm-intel-nextChris Wilson2010-11-151-0/+5
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_ringbuffer.c
| * | | | | agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | agp/intel: the GMCH is always enabled for integrated processor graphicsChris Wilson2010-10-311-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and trying to set the bit is ineffectual. Fixes the regression from e380f60 which detected that we were trying to do undefined operations on the I830_GMCH_CTRL. Reported-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | agp/intel: Sandybridge doesn't require GMCH enablingChris Wilson2010-10-291-7/+30
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | intel-gtt: maximize ggtt size on platforms that support thisDaniel Vetter2010-10-282-29/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VT-d supporting platforms the GGTT is allocated in a stolen mem section separate from graphcis stolen mem. The GMCH register contains a bitfield specifying the size of that region. Docs suggest that this region can only be used for GGTT and PPGTT. Hence ensure that the PPGTT is disabled and use the complete area for the GGTT. Unfortunately the graphics core on G33/Pineview can't cope with really large GTTs and the BIOS usually enables the maximum of 512MB. So don't bother with maximizing the GTT on these platforms. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | | | | intel-gtt: save PGETBL_CTL later in the setup processDaniel Vetter2010-10-281-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... and switch to a more classical store-reg-on-suspend, restore-on-resume way of doing things. Obviously this is just preparation for the future, the code is not there at all, yet. This is needed because the next patch adjusts this register and everything in it (not just the pagetable address) needs to be restored on resume. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | | | | | Merge branch 'x86-amd-nb-for-linus' of ↵Linus Torvalds2011-01-061-17/+16Star
|\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, cacheinfo: Cleanup L3 cache index disable support x86, amd-nb: Cleanup AMD northbridge caching code x86, amd-nb: Complete the rename of AMD NB and related code
| * | | | | x86, amd-nb: Cleanup AMD northbridge caching codeHans Rosenfeld2010-11-181-15/+14Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support more than just the "Misc Control" part of the northbridges. Support more flags by turning "gart_supported" into a single bit flag that is stored in a flags member. Clean up related code by using a set of functions (amd_nb_num(), amd_nb_has_feature() and node_to_amd_nb()) instead of accessing the NB data structures directly. Reorder the initialization code and put the GART flush words caching in a separate function. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
| * | | | | x86, amd-nb: Complete the rename of AMD NB and related codeHans Rosenfeld2010-11-181-16/+16
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not only the naming of the files was confusing, it was even more so for the function and variable names. Renamed the K8 NB and NUMA stuff that is also used on other AMD platforms. This also renames the CONFIG_K8_NUMA option to CONFIG_AMD_NUMA and the related file k8topology_64.c to amdtopology_64.c. No functional changes intended. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
* | | | | agp/intel: Fix missed cached memory flags setting in i965_write_entry()Chris Wilson2010-12-141-2/+9
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes regression from a6963596a13e62f8e65b1cf3403a330ff2db407c, that missed to set cached memory type in GTT entry. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | | | agp/intel: Fix wrong kunmap in i830_cleanup()Takashi Iwai2010-12-051-2/+4
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a missing NULL check and fix the wrong address passed to kunmap() in i830_cleanup(). Cc: stable@kernel.org Signed-off-by: Takashi Iwai <tiwai@suse.de> [danvet: added cc stable] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | | BKL: remove extraneous #include <smp_lock.h>Arnd Bergmann2010-11-171-1/+0Star
|/ / | | | | | | | | | | | | | | | | | | The big kernel lock has been removed from all these files at some point, leaving only the #include. Remove this too as a cleanup. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'drm-intel-fixes' of ↵Dave Airlie2010-11-091-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel * 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel: drm/i915: Fix LVDS fixed-mode regression from 219adae1 drm/i915/ringbuffer: Use the HEAD auto-reporting mechanism drm/i915: Avoid might_fault during pwrite whilst holding our mutex agp/intel: fix cache control for sandybridge agp/intel: restore cache behavior on sandybridge drm/i915; Don't apply Ironlake FDI clock workaround to Sandybridge drm/i915: Fix KMS regression on Sandybridge/CPT i915: reprogram power monitoring registers on resume drm/i915: SNB BLT workaround drm/i915: Fix the graphics frequency clamping at init and when IPS is active. drm/i915: Allow powersave modparam to be adjusted at runtime. drm/i915: Apply big hammer to serialise buffer access between rings drm/i915: opregion_setup: iounmap correct address drm/i915: Flush read-only buffers from the active list upon idle as well i915: signedness bug in check_overlay_src() drm/i915: Fix typo from "Enable DisplayPort Audio"
| * | agp/intel: fix cache control for sandybridgeZhenyu Wang2010-11-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | agp/intel: restore cache behavior on sandybridgeZhenyu Wang2010-11-041-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | This restores cache behavior for default AGP_USER_MEMORY as uncached, and leave default AGP_USER_CACHED_MEMORY as LLC only. I've seen different cache behavior on one sandybridge desktop CPU vs. another mobile CPU. Until we figure out how to detect the real cache config, restore back to the original behavior now. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
* | parisc-agp: fix missing slab.h includeKyle McMartin2010-10-291-0/+1
| | | | | | | | | | | | | | | | Commit 338e4fab added a missing kfree if the alloc_pci_dev failed but forgot to include <linux/slab.h> for the definition of kfree. Signed-off-by: Kyle McMartin <kyle@redhat.com>
* | Merge branch 'next' of ↵Linus Torvalds2010-10-281-0/+4
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6 * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6: parisc: add tty driver to PDC console drivers/parisc/iosapic.c: Remove unnecessary kzalloc cast parisc: remove homegrown L1_CACHE_ALIGN macro arch/parisc: Removing undead ifdef CONFIG_PA20 parisc: unwind - optimise linked-list searches for modules parisc: change to new flag variable drivers/char/agp/parisc-agp.c: eliminate memory leak parisc: kill __do_IRQ parisc: convert eisa interrupts to flow handlers parisc: convert gsc and dino pci interrupts to flow handlers parisc: convert suckyio interrupts to flow handlers parisc: convert iosapic interrupts to proper flow handlers parisc: convert cpu interrupts to proper flow handlers parisc: lay groundwork for killing __do_IRQ parisc: add prlimit64 syscall parisc: squelch warning when using dev_get_stats
| * drivers/char/agp/parisc-agp.c: eliminate memory leakJulia Lawall2010-10-221-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | alloc_pci_dev allocates some memory, so that memory should be freed before leaving the function in an error case. A simplified version of the semantic match that finds this problem is: (http://coccinelle.lip6.fr/) // <smpl> @r exists@ local idexpression x; expression E; identifier f1; iterator I; @@ x = alloc_pci_dev(...); <... when != x when != true (x == NULL || ...) when != if (...) { <+...x...+> } when != I (...) { <+...x...+> } ( x == NULL | x == E | x->f1 ) ...> * return ...; // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Dan Carpenter <error27@gmail.com> Dave Airlie <airlied@linux.ie> Cc: Helge Deller <deller@gmx.de> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Kyle McMartin <kyle@redhat.com>
* | Merge branch 'drm-core-next' of ↵Linus Torvalds2010-10-278-1094/+804Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits) vmwgfx: Implement a proper GMR eviction mechanism drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2 drm/radeon/kms: properly compute group_size on 6xx/7xx drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker drm/radeon/kms/evergreen: set the clear state to the blit state drm/radeon/kms: don't poll dac load detect. gpu: Add Intel GMA500(Poulsbo) Stub Driver drm/radeon/kms: MC vram map needs to be >= pci aperture size drm/radeon/kms: implement display watermark support for evergreen drm/radeon/kms/evergreen: add some additional safe regs v2 drm/radeon/r600: fix tiling issues in CS checker. drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 ... Fix up conflicts in - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the new simplified stack-based kmap_atomic() interface - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL removal cleanups.
| * | agp/intel: Restore valid PTE bit for Sandybridge after bdd3072Chris Wilson2010-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | agp/intel: Also add B43.1 to list of supported devicesChris Wilson2010-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This was a missing piece from 41a5142 that dropped recognition of the AGP module for the second B43 variant. Reported-by: Stefan Bader <stefan.bader@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| * | agp/amd-k7: Allow binding user memory to the AGP GART.Francisco Jerez2010-10-191-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TTM-based DRM drivers need to be able to bind user memory to the AGP aperture. This patch fixes the "[TTM] AGP Bind memory failed." errors and the subsequent fallout seen with the nouveau driver. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Grzesiek Sójka <pld@pfu.pl> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | some clean up to intel-gtt.cJan Beulich2010-09-241-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit e517a5e97080bbe52857bd0d7df9b66602d53c4d the call to map_page_into_agp() got removed from intel_i830_setup_flush(), but the counterpart call from intel_i830_fini_flush() to unmap_page_from_agp() was left in place. Additionally, the page allocated here never gets its physical address used for sending to hardware, so there's no need to allocate it with GFP_DMA32. Nor is __GFP_ZERO really necessary, as the page is used only to store data to force flushing of some internal processor state. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt add a cleanup function for chipset specific stuffDaniel Vetter2010-09-211-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | The old code didn't clean up the i830 chipset flush page. And it looks nicer. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: store the dma mask size in intel_gtt_driverDaniel Vetter2010-09-211-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | Storing this explicitly makes for clearer code and hopefully less further confusion. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: clean up gtt size reportingDaniel Vetter2010-09-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Consolidate everything in intel-gtt.c and also kill the export of intel_max_stolen. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | agp: kill agp_(unmap|map)_memoryDaniel Vetter2010-09-212-11/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DMA remapping was only used by the intel-gtt driver. With that code now folded into the driver, kill the agp generic support for it. Cc: Dave Airlie <airlied@linux.ie> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: consolidate fake_agp driver structsDaniel Vetter2010-09-211-131/+39Star
| | | | | | | | | | | | | | | | | | | | | They're now all the same. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: move chipset flush to the gtt driver structDaniel Vetter2010-09-211-7/+21
| | | | | | | | | | | | | | | | | | | | | This is the last differentiator between the different fake agp drivers. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: kill mask_memory functionsDaniel Vetter2010-09-211-92/+13Star
| | | | | | | | | | | | | | | | | | | | | | | | That indirection mess can now go. Add a dummy i81x gtt_driver to avoid a NULL pointer check. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: generic (insert|remove)_entries for sandybridgeDaniel Vetter2010-09-211-136/+8Star
| | | | | | | | | | | | | | | | | | | | | | | | Like before, but now with the added bonus of being able to kill quite a bit of no-longer userful code (the old dmar support stuff). Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| * | intel-gtt: generic (insert|remove)_entries for g33/i965Daniel Vetter2010-09-211-12/+9Star
| | | | | | | | | | | | | | | | | | | | | Like for the i915. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-17 06:12:47 +0200