openslx/kernel-qcow2-linux.git - In-kernel qcow2 (Kernel part)

	Commit message (Collapse)	Author	Age	Files	Lines
*	clk: hisi: add hisi_clk_register_gate	Zhangfei Gao	2014-05-12	1	-0/+28
\| \| \| \| \| \| \|	Add hisi_clk_register_gate register clk gate table Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
*	clk: hisi: use clk_register_mux_table in hisi_clk_register_mux	Zhangfei Gao	2014-05-12	1	-5/+8
\| \| \| \| \| \| \|	Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
*	clk: hisi: remove static variable	Haojian Zhuang	2014-03-19	1	-17/+47
\| \| \| \| \| \| \|	Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
*	clk: hisi: assign missing clk to table	Haojian Zhuang	2014-03-19	1	-0/+2
\| \| \| \| \| \|	The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
*	clk: hisilicon: add common clock support	Haojian Zhuang	2013-12-04	1	-0/+171
	Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>