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* Merge tag 'imx-clk-fixes-4.6-2' of ↵Stephen Boyd2016-05-122-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull some non-critical i.MX clk fixes from Shawn Guo: * Fix the commit 3713e3f5e927 ("clk: imx35: define two clocks for rtc") which messed up the clock enumeration when adding new clock. * tag 'imx-clk-fixes-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: imx35: restore existing used clock enumeration clk: imx6q: fix typo in CAN clock definition
| * ARM: dts: imx35: restore existing used clock enumerationAlexander Kurz2016-04-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new element got inserted into enum mx35_clks with commit 3713e3f5e927 ("clk: imx35: define two clocks for rtc"). This insertion shifted most nummerical clock assignments to a new nummerical value which in turn rendered most hardcoded nummeric values in imx35.dtsi incorrect. Restore the existing order by moving the newly introduced clock to the end of the enum. Update the dts documentation accordingly. Signed-off-by: Alexander Kurz <akurz@blala.de> Fixes: 3713e3f5e927 ("clk: imx35: define two clocks for rtc") Cc: <stable@vger.kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx6q: fix typo in CAN clock definitionLothar Waßmann2016-04-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit ee36027427c7 ("clk: imx: Add clock support for imx6qp") introduced a regression due to a subtle typo in the 'can_root' clock definition. The effect is that trying to configure the bitrate of the can interfaces fails with -EDOM or produces a division by zero error due to the clock_freq of the can serial clock being reported as '0'. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Fixes: ee36027427c7 ("clk: imx: Add clock support for imx6qp") Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx7d: fix ahb clock mux 1Stefan Agner2016-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: return correct frequency for Ethernet PLLStefan Agner2016-04-271-1/+8
| | | | | | | | | | | | | | | | | | The i.MX 7 designs Ethernet PLL provides a 1000MHz reference clock. Store the reference clock in the clk_pllv3 structure according to the PLL type. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: vf610: add TCON ipg clockStefan Agner2016-04-121-0/+3
| | | | | | | | | | | | | | | | | | Add the ipg (bus) clock for the TCON modules (Timing Controller). This module is required by the new DCU DRM driver, since the display signals pass through TCON. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: vf610: fix DCU clock treeStefan Agner2016-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy mixes the bus clock with the display controllers pixel clock. Tests have shown that the gates in CCM_CCGR3/9 registers do not control the DCU pixel clock, but only the register access clock (bus clock). Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus clock (ipg_bus). Since the clock has not been used far, there are no further changes needed. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: add ckil clock for i.MX7Gary Bisson2016-04-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | Add the necessary clock to use the ckil on i.MX7. Inspired from the following patch: https://github.com/boundarydevices/linux-imx6/commit/b80e8271 Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: vf610: add suspend/resume supportStefan Agner2016-03-311-0/+48
| | | | | | | | | | | | | | | | | | | | The clock register are lost when enterying LPSTOPx, hence provide suspend/resume functions restoring them. The clock gates get restored by the individual driver, hence we do not need to restore them here. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: vf610: add WKPU unitStefan Agner2016-03-311-0/+2
| | | | | | | | | | | | Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: vf610: leave DDR clock onStefan Agner2016-03-311-0/+3
| | | | | | | | | | | | | | | | | | | | To use STOP mode without putting DDR3 into self-refresh mode, we need to keep the DDR clock enabled. Use the new gate configuration with a value of 2 to make sure that the clock is enabled in RUN, WAIT and STOP mode. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: clk-gate2: allow custom gate configurationStefan Agner2016-03-312-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx6sx: Register SAI clocks as shared clocksFabio Estevam2016-03-311-4/+6
|/ | | | | | | | SAIx and SAIx_IPG share the same bit fields in the CCM registers, so we should better register them via imx_clk_gate2_shared(). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* clk: imx: Remove CLK_IS_ROOTStephen Boyd2016-03-031-1/+1
| | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'imx-clk-4.6' of ↵Stephen Boyd2016-03-022-59/+138
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clk updates from Shawn Guo: The i.MX clock update for 4.6: - Add the clock driver support for the latest i.MX6 family SoCs addition - i.MX6QP. - Clean up the whitespace in i.MX6UL clock driver and add the missing KPP clock. - Correct pwm7 clock name in i.MX6UL clock driver. * tag 'imx-clk-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: add kpp clock for i.MX6UL clk: imx: whitespace cleanup; no functional change clk: imx: correct pwm7 clock name in driver for i.MX6UL clk: imx: Add clock support for imx6qp
| * clk: imx: add kpp clock for i.MX6ULLothar Waßmann2016-02-281-0/+1
| | | | | | | | | | | | | | | | Add the necessary clock to use the KPP interface on i.MX6UL. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: whitespace cleanup; no functional changeLothar Waßmann2016-02-281-31/+31
| | | | | | | | | | | | | | | | remove whitespace before TAB. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: correct pwm7 clock name in driver for i.MX6ULAnatolij Gustschin2016-02-181-1/+1
| | | | | | | | | | | | | | | | Don't capitalize p in the pwm7 clock name. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: Add clock support for imx6qpBai Ping2016-02-141-27/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | most of the clock tree structures on i.MX6 Quad Plus are same as on i.MX6Q. there still some differences between these two SOCs. compared to the i.XM6Q, the differents of clocks on i.MX6QP is mainly on: 1. New clock gate added to support the PRE and PRG modules 2. 24MHz OSC clock option added to the UART, IPG, ECSPI, and CAN clock roots. 3. MMDC channel 1 clock gate is now controllable. 4. clock gating added to the LDB_DIx_IPU clocks on i.MX6QP 5. EMI clock root divider fix 6. other updates fo CSCMRx, CSCDRx and CS2CDR registers. detailed infomation, please refer to the i.MX6QP RM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang2016-01-294-8/+5Star
|/ | | | | | | | | | to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-nextMichael Turquette2015-12-226-28/+30
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| * Merge tag 'imx-clk-v4.5' of ↵Michael Turquette2015-12-226-28/+30
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next The i.MX clock updates for 4.5: - Add is_prepared function callback for pllv3 clock driver - Use imx_check_clocks() on imx6ul and imx7d clock drivers to save some code - Add a core clock for imx7d to support generic cpufreq driver - Support imx6q clock routing with OSC to anaclk2/2b - To support more precise pixel clocks on imx5, allow ipu_di_sel clock selectors to influence the PLLs that they are derived from - A cleanup on imx25 OSC clock
| | * clk: imx5: ipu_di_sel clocks can set parent ratesPatrick Brünn2015-12-021-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To obtain exact pixel clocks, allow the DI clock selectors to influence the PLLs that they are derived from. Commit 4591b13289b5 ("ARM: i.MX6: ipu_di_sel clocks can set parent rates") did this for i.MX6. Port it to enable high display resolutions on i.MX53 based platforms such as CX9020 Embedded PC, too. Signed-off-by: Patrick Brünn <p.bruenn@beckhoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: Replace clk error check with imx_check_clocks()Bai Ping2015-12-022-7/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | As we already have a 'imx_check_clocks' to do the clock error check, so cleanup the error check code. Signed-off-by: Bai Ping <b51503@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: Add a virtual arm clk on i.mx7dBai Ping2015-12-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a virtual arm clk to abstract the actual steps when changing the ARM core frequency.So we can using the 'cpufreq-dt' driver on i.MX7D/Solo. Signed-off-by: Bai Ping <b51503@freescale.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: clk-imx6q: Let OSC to be routed to anaclk2/2bMichael Trimarchi2015-11-251-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OSC can be used as USB hub source clock. An example we can route to CLK2_P imx6 pin. This show a usage example: [...] usb_hub: usb-hub { compatible = "smsc,usb3503a"; clocks = <&clks IMX6QDL_CLK_LVDS2_GATE>; clock-names = "refclk"; }; }; [...] &clks { assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>; }; /sys/kernel/debug/clk/clk_summary osc 5 5 24000000 0 0 [...] lvds2_sel 1 1 24000000 0 0 lvds2_gate 1 1 24000000 0 0 [...] Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: add 'is_prepared' clk_ops callback for pllv3 clkBai Ping2015-11-251-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'is_prepared' callback function for pllv3 type clk to make sure when the system is bootup, the unused clk is in a known state to match the prepare count info. Signed-off-by: Bai Ping <b51503@freescale.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx25: Remove osc clock from driverMarkus Pargmann2015-11-251-16/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'osc' clock is already initialized by the fixed clock defined in imx25.dtsi. The imx25 clock driver tries to add this clock for a second time and fails with -EEXIST: i.MX clk 1: register failed with -17 As the clock is already properly setup in DT with a different driver, we can completely remove the handling in the imx25 clock driver. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | | Merge tag 'fixes-for-linus' of ↵Linus Torvalds2015-12-131-4/+4
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Arnd Bergmann: "Here are a bunch of small bug fixes for various ARM platforms, nothing really sticks out this week, most of either fixes bugs in code that was just added in 4.4, or that has been broken for many years without anyone noticing. at91/sama5d2: - fix sama5de hardware setup of sd/mmc interface - proper selection of pinctrl drivers. PIO4 is necessary for sama5d2 berlin: - fix incorrect clock input for SDIO exynos: - Fix potential NULL pointer dereference in Exynos PMU driver. imx: - Fix vf610 SAI clock configuration bug which is discovered by the newly added master mode support in SAI audio driver. - Fix buggy L2 cache latency values in vf610 device trees, which may cause system hang when cpu runs at a higher frequency. ixp4xx: - fix prototypes for readl/writel functions ls2080a: - use little-endian register access for GPIO and SDHCI omap: - Fix clock source for ARM TWD and global timers on am437x - Always select REGULATOR_FIXED_VOLTAGE for omap2+ instead of when MACH_OMAP3_PANDORA is selected - Fix SPI DMA handles for dm816x as only some were mapped - Fix up mbox cells for dm816x to make mailbox usable pxa: - use PWM lookup table for all ezx machines s3c24xx: - Remove incorrect __init annotation from s3c24xx cpufreq driver structures. versatile: - fix PCI IRQ mapping on Versatile PB" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ls2080a/dts: Add little endian property for GPIO IP block dt-bindings: define little-endian property for QorIQ GPIO ARM64: dts: ls2080a: fix eSDHC endianness ARM: dts: vf610: use reset values for L2 cache latencies ARM: pxa: use PWM lookup table for all machines ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1 ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock ARM: dts: am4372: fix clock source for arm twd and global timers ARM: at91: fix pinctrl driver selection ARM: at91/dt: add always-on to 1.8V regulator ARM: dts: vf610: fix clock definition for SAI2 ARM: imx: clk-vf610: fix SAI clock tree ARM: ixp4xx: fix read{b,w,l} return types irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE ARM: dts: add dm816x missing spi DT dma handles ARM: dts: add dm816x missing #mbox-cells cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init ARM: EXYNOS: Fix potential NULL pointer access in exynos_sys_powerdown_conf
| * | ARM: imx: clk-vf610: fix SAI clock treeStefan Agner2015-12-021-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Synchronous Audio Interface (SAI) instances are clocked by independent clocks: The bus clock and the audio clock (as shown in Figure 51-1 in the Vybrid Reference Manual). The clock gates in CCGR0/CCGR1 for SAI0 through SAI3 are bus clock gates, as access tests to the registers with/without gating those clocks have shown. The audio clock is gated by the SAIx_EN gates in CCM_CSCDR1, followed by a clock divider (SAIx_DIV). Currently, the parent of the bus clock gates has been assigned to SAIx_DIV, which is not involved in the bus clock path for the SAI instances (see chapter 9.10.12, SAI clocking in the Vybrid Reference Manual). Fix this by define the parent clock of VF610_CLK_SAIx to be the bus clock. If the driver needs the audio clock (when used in master mode), a fixed device tree is required which assign the audio clock properly to VF610_CLK_SAIx_DIV. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | imx/clk-pllv2: fix wrong do_div() usageNicolas Pitre2015-11-301-4/+5
| | | | | | | | | | | | | | | | do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | imx/clk-pllv1: fix wrong do_div() usageNicolas Pitre2015-11-301-7/+7
|/ | | | | | | | do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: imx31: add missing of_node_putJulia Lawall2015-10-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_compatible_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e; @@ for_each_compatible_node(n,...) { ... ( of_node_put(n); | e = n | + of_node_put(n); ? break; ) ... } ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: imx27: add missing of_node_putJulia Lawall2015-10-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_compatible_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e; @@ for_each_compatible_node(n,...) { ... ( of_node_put(n); | e = n | + of_node_put(n); ? break; ) ... } ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'imx-clk-4.4' of ↵Stephen Boyd2015-10-1613-31/+209
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX updates from Shawn Guo: "The i.MX clock updates for 4.4: - A couple of fixes on i.MX31 and i.MX35 clock initialization functions which makes mxc_timer_init() currently be called twice for DT boot. - Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal design target. - Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for Vybrid, and SPDIF_GCLK for i.MX6. - A series from Lucas to fix early debug UART clock setup. This is currently a one-off fix for i.MX platform, and can be extended to become a generic solution later." * tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx6: Add SPDIF_GCLK clock in clock tree clk: imx7d: add ADC root clock clk: imx31: Do not call mxc_timer_init twice when booting with DT clk: imx7d: retain early UART clocks during kernel init clk: imx6: retain early UART clocks during kernel init clk: imx5: retain early UART clocks during kernel init clk: imx35: retain early UART clocks during kernel init clk: imx31: retain early UART clocks during kernel init clk: imx27: retain early UART clocks during kernel init clk: imx25: retain early UART clocks during kernel init clk: imx: add common logic to detect early UART usage clk: imx35: Do not call mxc_timer_init twice when booting with DT clk: clk-vf610: Add clock for Vybrid OCOTP controller clk: imx: increase AXI clock rate to 264MHz for i.MX6UL
| * clk: imx6: Add SPDIF_GCLK clock in clock treeShengjiu Wang2015-10-123-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also one clock of SPDIF, which is missed before. We found an issue that imx can't enter low power mode with spdif if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because spdif driver will register IMX6x_CLK_SPDIF clock to regmap, regmap will do clk_prepare in init function, then IMX6x_CLK_SPDIF clock is prepared in probe, so its parent clock (PLL clock) is prepared, the prepare operation of PLL clock is to enable the clock. But I.MX needs all PLL clock is disabled, then it can enter low power mode. So we can't use IMX6x_CLK_SPDIF as the core clock of spdif, the correct spdif core clock is SPDIF_GCLK, which share same gate bit with IMX6x_CLK_SPDIF clock. SPDIF_GCLK's parent clock is ipg clock. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx7d: add ADC root clockHaibo Chen2015-10-091-0/+1
| | | | | | | | | | | | | | | | Add ADC root clock support in imx7d clock tree. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx31: Do not call mxc_timer_init twice when booting with DTAlexander Stein2015-09-301-8/+17
| | | | | | | | | | | | | | | | | | | | mxc_timer_init must not be called from within mx31_clocks_init_dt. It will eventually be called by imx31_timer_init_dt (drivers/clocksource/timer-imx-gpt.c). This arranges the initialization code similar to clk-imx27.c Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx7d: retain early UART clocks during kernel initLucas Stach2015-09-261-0/+13
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx6: retain early UART clocks during kernel initLucas Stach2015-09-263-0/+24
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx5: retain early UART clocks during kernel initLucas Stach2015-09-261-0/+16
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx35: retain early UART clocks during kernel initLucas Stach2015-09-261-0/+10
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx31: retain early UART clocks during kernel initLucas Stach2015-09-261-0/+12
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx27: retain early UART clocks during kernel initLucas Stach2015-09-261-0/+13
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx25: retain early UART clocks during kernel initLucas Stach2015-09-261-0/+12
| | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: add common logic to detect early UART usageLucas Stach2015-09-262-0/+39
| | | | | | | | | | | | | | | | | | | | | | Both earlycon and eralyprintk depend on the bootloader setup UART clocks being retained. This patch adds the common logic to detect such situations and make the information available to the clock drivers, as well as adding the facilities to disable those clocks at the end of the kernel init. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx35: Do not call mxc_timer_init twice when booting with DTAlexander Stein2015-09-231-22/+27
| | | | | | | | | | | | | | | | | | | | mxc_timer_init must not be called from within mx35_clocks_init_dt. It will eventually be called by imx31_timer_init_dt (drivers/clocksource/timer-imx-gpt.c). This arranges the initialization code similar to clk-imx27.c Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: clk-vf610: Add clock for Vybrid OCOTP controllerSanchayan Maity2015-09-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock support for Vybrid On-Chip One Time Programmable (OCOTP) controller. While the OCOTP block does not require explicit clock gating, for programming the OCOTP timing register the clock rate of ipg clock is required for timing calculations related to fuse and shadow register read sequence. We explicitly specify the ipg clock for OCOTP as a result. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: increase AXI clock rate to 264MHz for i.MX6ULAnson Huang2015-09-171-0/+18
| | | | | | | | | | | | | | | | | | | | | | On i.MX6UL, AXI clock rate's design target is 264MHz, but by default it is only set to 198MHz which is NOT good enough for performance, this patch increases AXI clock rate from 198MHz to 264MHz to meet the design target, this is done by switching its parent clock "periph" from 396MHz PFD to 528MHz PLL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: imx: use sign_extend32() and abs()Martin Kepplinger2015-10-021-8/+4Star
|/ | | | | | | | | This simplifies the given function by getting rid of the manual sign extension as well as saving an absolute value in an extra variable. Signed-off-by: Martin Kepplinger <martink@posteo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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