| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: mmp: Convert to clk_hw based provider APIs | Stephen Boyd | 2015-08-25 | 1 | -2/+1 |
| | | | | | | | | | We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Cc: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> | ||||
| * | clk: mmp: add mmp private gate clock | Chao Xie | 2014-11-13 | 1 | -0/+133 |
| Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is to disable when write register. So we have to define the "mask", "enable_val", "disable_val" for this kind of gate clock. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org> | |||||
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| In-kernel qcow2 (Kernel part) | OpenSLX |
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