summaryrefslogtreecommitdiffstats
path: root/drivers/clk/mmp
Commit message (Collapse)AuthorAgeFilesLines
* clk: mmp: add timer clock for pxa168/mmp2/pxa910Chao Xie2015-06-043-0/+24
| | | | | | | | Timer has external fast clock, and it is a mux clock. Add the timer clock type for timer driver. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mmp: Fix the wrong factor table for uart PLLChao Xie2015-06-042-6/+2Star
| | | | | | | | | | The suggested value in the mmp2 manual is wrong. There are only 13 bits for numerator, but some suggested value has 14 bits. Fix the factor tabled and remove the unused items. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168Chao Xie2015-06-042-0/+2
| | | | | | | USB will drive clock from USB_PLL. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mmp: add PXA1928 clock supportRob Herring2015-05-152-0/+267
| | | | | | | | | | | | | Add initial clock support for Marvell PXA1928. The PXA1928 is a mobile SOC and is similar to other MMP/PXA series of SOCs, so a lot of the existing infrastructure is reused here. Currently the PLLs are just fixed clocks, and not all leaf clocks are implemented. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mmp: Silence sparse warningsStephen Boyd2015-05-152-2/+2
| | | | | | | | drivers/clk/mmp/clk-apbc.c:118:16: warning: symbol 'clk_apbc_ops' was not declared. Should it be static? drivers/clk/mmp/clk-apmu.c:64:16: warning: symbol 'clk_apmu_ops' was not declared. Should it be static? Cc: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Add rate constraints to clocksTomeu Vizoso2015-02-021-0/+2
| | | | | | | | | | | | | | | | Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
* clk: mmp: fix sparse non static symbol warningWei Yongjun2014-12-111-1/+1
| | | | | | | | | | Fixes the following sparse warnings: drivers/clk/mmp/clk-frac.c:113:6: warning: symbol 'clk_factor_init' was not declared. Should it be static? Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-041-2/+2
| | | | | | | | This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add mmp2 DT support for clock driverChao Xie2014-11-132-0/+335
| | | | | | | | It adds the DT support for mmp2 clock subsystem. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add pxa910 DT support for clock driverChao Xie2014-11-132-1/+302
| | | | | | | | It adds the DT support for pxa910 clock subsystem. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add pxa168 DT support for clock driverChao Xie2014-11-132-0/+281
| | | | | | | | It adds the DT support for pxa168 clock subsystem. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add reset supportChao Xie2014-11-133-0/+132
| | | | | | | | | | | Some clock control regsiter has bit to reset the cotroller. So before enable the clock, we need deassert the reset pin. Make use of reset controller framework to export reset interface for device drivers, then device driver can control the reset action. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add basic support functions for DT supportChao Xie2014-11-133-2/+298
| | | | | | | | | | In order to support DT for mmp SOC clocks, it defines some basic APIs which are shared by all mmp SOC clock units. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add mmp private gate clockChao Xie2014-11-133-1/+155
| | | | | | | | | | | | | | Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is to disable when write register. So we have to define the "mask", "enable_val", "disable_val" for this kind of gate clock. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add clock type mixChao Xie2014-11-133-1/+580
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock type mix is a kind of clock combines "div" and "mux". This kind of clock can not allow to change div first then mux or change mux first or div. The reason is 1. Some clock has frequency change bit. Each time want to change the frequency, there are some operations based on this bit, and these operations are time-cost. Seperating div and mux change will make the process longer, and waste more time. 2. Seperting the div and mux may generate middle clock that the peripharals do not support. It may make the peripharals hang. There are three kinds of this type of clock in all SOCes. 1. The clock has bit to trigger the frequency change. 2. Same as #1, but the operations for the bit is different 3. Do not have frequency change bit. So this type of clock has implemented the callbacks ->determine_rate ->set_rate_and_parent These callbacks can help to change the div and mux together. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: move definiton of mmp_clk_frac to clk.hChao Xie2014-11-132-18/+22
| | | | | | | | | | Move the definition of structure of mmp_clk_frac to clk.h. So device tree support can use this structure. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add init callback for clk-fracChao Xie2014-11-131-0/+40
| | | | | | | | | | For the clk-frac, we need to make sure that the initial clock rate is one item of the table. If it is not, we use the first item in the table by default. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add spin lock for clk-fracChao Xie2014-11-135-5/+15
| | | | | | | | | | | The register used by clk-frac may be shared with other clocks. So it needs to use spin lock to protect the register access. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: add prefix "mmp" for structures defined for clk-fracChao Xie2014-11-135-21/+22
| | | | | | | | | | | The structures defined for clk-frac will be used out side of clk-frac.c. To avoid conflicts, add prefix "mmp" for these structures' name. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: mmp: try to use closer one when do round rateChao Xie2014-03-271-3/+7
| | | | | | | | | | | | The orignal code will use the bigger rate between "previous rate" and "current rate" when caculate the rate. In fact, hardware cares about the closest one. So choose the closer rate between "previous rate" and "current rate". Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: fix the wrong calculation formulaChao Xie2014-03-271-5/+5
| | | | | | | | | | | The formula is numerator/denominator = Fin / (Fout * factor) So Fout = Fin * denominator / (numerator * factor). Current clk_factor_round_rate and clk_factor_recalc_rate use wrong formula. This patch will fix them. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: fix wrong mask when calculate denominatorChao Xie2014-03-271-1/+1
| | | | | | | | The code has typo when calculate denominator. It should use den_mask instead of num_mask. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-193-38/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* ARM: pxa: remove cpu_is_xxx in gpio driverHaojian Zhuang2013-04-113-3/+3
| | | | | | | | Avoid to use cpu_is_xxx() in pxa gpio driver. Use platform_device_id to identify the difference. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* clk: mmp: add clock definition for mmp2Chao Xie2012-08-282-0/+450
| | | | | | | | | Initialize the clocks for mmp2 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: add clock definition for pxa910Chao Xie2012-08-282-0/+321
| | | | | | | | | Initialize the clocks for pxa910 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: add clock definition for pxa168Chao Xie2012-08-282-0/+348
| | | | | | | | | Initialize the clocks for pxa168 Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mmp: add mmp specific clocksChao Xie2012-08-285-0/+442
add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-21 06:37:17 +0200