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* clk: qcom: fix platform_no_drv_owner.cocci warningskbuild test robot2015-02-251-1/+0Star
| | | | | | | | | | | | drivers/clk/qcom/lcc-msm8960.c:577:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: fix platform_no_drv_owner.cocci warningskbuild test robot2015-02-251-1/+0Star
| | | | | | | | | | | | | drivers/clk/qcom/lcc-ipq806x.c:465:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci CC: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: Add PLL4 vote clockStephen Boyd2015-02-251-0/+13
| | | | | | | This clock is needed for most audio clock frequencies. Add it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: lcc-msm8960: Fix PLL rate detectionStephen Boyd2015-02-251-1/+1
| | | | | | | | | | regmap_read() returns 0 on success, not the value of the register that is read. Fix it so we properly detect the frequency plan. Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: Fix slimbus n and m val offsetsStephen Boyd2015-02-251-2/+2
| | | | | | | | | | These shifts were copy/pasted from the pcm which is a different size RCG. Use the correct offsets so that slimbus rates are correct. Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: Add rate constraints to clocksTomeu Vizoso2015-02-023-2/+15
| | | | | | | | | | | | | | | | Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
* clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driverStephen Boyd2015-01-273-0/+595
| | | | | | | | | Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: Add IPQ806X LPASS clock controller (LCC) driverRajendra Nayak2015-01-274-0/+495
| | | | | | | | | | | | | | | | Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and pcm clocks. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> [sboyd@codeaurora.org: Reworded commit text, added Kconfig select, fleshed out Kconfig description a bit more, added pll4 configuration and reworked probe for it, added muxes, split out dt-binding file] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: Add simple regmap based muxesStephen Boyd2015-01-273-0/+89
| | | | | | | | | | | Add support for muxes that use regmap instead of readl/writel directly. We don't support as many features as clk-mux.c, but this is good enough to support getting and setting parents. Adding a table based lookup can be added in the future if needed. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: qcom: Add support for regmap divider clocksJosh Cartwright2015-01-273-0/+100
| | | | | | | | | | | | Add support for dividers that use regmap instead of readl/writel. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Switch to using generic divider code, drop enable/disable, reword commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds2014-12-213-20/+30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
| * clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-043-20/+30
| | | | | | | | | | | | | | | | This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-155-5/+0Star
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * clk: qcom: drop owner assignment from platform_driversWolfram Sang2014-10-205-5/+0Star
| | | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | clk: qcom: Fix duplicate rbcpr clock nameGeorgi Djakov2014-11-171-1/+1
|/ | | | | | | | | | | | | There is a duplication in a clock name for apq8084 platform that causes the following warning: "RBCPR_CLK_SRC" redefined Resolve this by adding a MMSS_ prefix to this clock and making its name coherent with msm8974 platform. Fixes: 2b46cd23a5a2 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support") Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* Merge tag 'qcom-clocks-for-3.18' of ↵Mike Turquette2014-09-279-88/+219
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next qcom clock changes for 3.18 Some fixes for the IPQ driver and some code consolidation and refactoring.
| * clk: qcom: Add support for banked MD RCGsStephen Boyd2014-09-233-56/+77
| | | | | | | | | | | | | | | | | | The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add support for setting rates on PLLsStephen Boyd2014-09-232-1/+87
| | | | | | | | | | | | | | Some PLLs may require changing their rate at runtime. Add support for these PLLs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Consolidate frequency finding logicStephen Boyd2014-09-234-32/+27Star
| | | | | | | | | | | | | | | | | | There are two find_freq() functions in clk-rcg.c and clk-rcg2.c that are almost exactly the same. Consolidate them into one function to save on some code space. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add IPQ8064 PLL required for USBAndy Gross2014-09-231-1/+30
| | | | | | | | | | | | | | | | | | This patch adds the PLL0 that is required for the USB clocks to work properly. Signed-off-by: Andy Gross <agross@codeaurora.org> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Remove .owner field for driverKiran Padwal2014-09-263-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: qcom: Fix sdc 144kHz frequency entryStephen Boyd2014-09-031-1/+1
|/ | | | | | | | | | | | | | The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable. Cc: Kumar Gala <galak@codeaurora.org> Cc: Andy Gross <agross@codeaurora.org> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'qcom-clocks-for-3.17' of ↵Mike Turquette2014-07-2614-80/+10568
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm qcom clock changes for 3.17 These patches add support for a handful of Qualcomm's SoC clock controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064. There's also a small collection of bug fixes that aren't critical -rc worthy regressions because the consumer drivers aren't present or using the buggy clocks and one optimization for HDMI.
| * clk: qcom: Add support for APQ8064 multimedia clocksStephen Boyd2014-07-161-2/+431
| | | | | | | | | | | | | | | | | | | | The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: pll: Add support for configuring SR PLLsStephen Boyd2014-07-162-3/+14
| | | | | | | | | | | | | | | | Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on apq8064. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: mdp_lut_clk is a child of mdp_srcStephen Boyd2014-07-161-1/+1
| | | | | | | | | | | | | | | | The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the child of the mdp_src clock. Fix it. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Fix PLL rate configurationsStephen Boyd2014-07-163-17/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Fix MN frequency tables, parent map, and jpegdStephen Boyd2014-07-161-40/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clocks that don't have a pre-divider don't list any pre-divider in their frequency tables, but their tables are initialized using aggregate initializers. Use tagged initializers so we properly assign the m and n values for each frequency. Furthermore, the mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second element to pll2 instead of pll8, causing the clock driver to recalculate the wrong rate for any clocks using this array along with a rate that uses pll2. Plus the .num_parents field is 3 instead of 4 so you can't even switch the parent to pll3. Finally I noticed that the jpegd clock improperly indicates that the pre-divider width is only 2, when it's actually 4 bits wide. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Support bypass RCG configurationStephen Boyd2014-07-163-14/+47
| | | | | | | | | | | | | | | | | | | | | | In the case of HDMI clocks, we want to bypass the RCG's ability to divide the output clock and pass through the parent HDMI PLL rate. Add a simple set of clk_ops to configure the RCG to do this. This removes the need to keep adding more frequency entries to the tv_src clock whenever we want to support a new rate. Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add support for IPQ8064's global clock controller (GCC)Kumar Gala2014-07-163-0/+2433
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the global clock controller found on IPQ8064 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. This is currently missing clocks for USB HSIC and networking devices. Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) supportGeorgi Djakov2014-07-163-0/+3362
| | | | | | | | | | | | | | | | | | | | Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add APQ8084 clocks for SATA, PCIe and UFSGeorgi Djakov2014-07-111-0/+667
| | | | | | | | | | | | | | | | | | Add the necessary clocks for SATA, PCIe and UFS to the APQ8084 global clock controller (GCC). This will allow the above device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add APQ8084 Global Clock Controller supportGeorgi Djakov2014-07-113-0/+2953
| | | | | | | | | | | | | | | | This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Fully support apq8064 global clock controlStephen Boyd2014-07-111-4/+569
| | | | | | | | | | | | | | Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: add clocks necessary for apq8064 sdccSrinivas Kandagatla2014-07-111-0/+12
| | | | | | | | | | | | | | | | | | This patch adds clocks necessary for SD card controller on apq8064 SOC. Without this patch the clocks are not visible to the sdcc driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: HDMI source sel is 3 not 2Stephen Boyd2014-07-031-1/+1
|/ | | | | | | | | | The HDMI PLL input to the tv mux is supposed to be 3, not 2. Fix the code so that we can properly select the HDMI PLL. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Reported-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Return error pointers for unimplemented clocksStephen Boyd2014-05-291-1/+3
| | | | | | | | | | | Not all clocks are implemented but client drivers can still request them. Currently we will return a NULL pointer to them if the clock isn't implemented in software but NULL pointers are valid clock pointers. Return an error pointer so that driver's don't proceed without a clock they may actually need. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Support msm8974pro global clock control hardwareStephen Boyd2014-05-291-6/+124
| | | | | | | | | A new PLL (gpll4) is added on msm8974 PRO devices to support a faster sdc1 clock rate. Add support for this and the two new sdcc cal clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Properly support display clocks on msm8974Stephen Boyd2014-05-291-51/+54
| | | | | | | | | | | | The display clocks all source from dedicated phy PLLs within their respective multimedia hardware block. Hook up these PLLs to the display clocks with the appropriate parent mappings, clock flags, and the appropriate clock ops. This should allow the display clocks to work once the appropriate phy PLL driver registers their PLL clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Support display RCG clocksStephen Boyd2014-05-292-15/+287
| | | | | | | | | Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Return highest rate when round_rate() exceeds planStephen Boyd2014-05-291-1/+2
| | | | | | | | | | | | Some drivers may want to call clk_set_rate() with a very large number to force the clock to go as fast as it possibly can without having to know the range between the highest rate and second highest rate. Add support for this by defaulting to the highest rate in the frequency table if we can't find a frequency greater than what is requested. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix mmcc-8974's PLL configurationsStephen Boyd2014-05-291-5/+8
| | | | | | | | | | We forgot to add the status bit for the PLLs and we were using the wrong register and masks for configuration, leading to unexpected PLL configurations. Fix this. Fixes: d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix clk_rcg2_is_enabled() checkStephen Boyd2014-05-291-1/+1
| | | | | | | | | If the bit is set the clock is off so we should be checking for a clear bit, not a set bit. Invert the logic. Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix blsp2_ahb_clk register offsetGeorgi Djakov2014-05-241-1/+1
| | | | | | | | The address of the blsp2_ahb_clk register is incorrect. Fix it. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix msm8660 GCC probeStephen Boyd2014-05-171-0/+12
| | | | | | | | | | When consolidating the msm8660 GCC probe code I forgot to keep around these temporary clock registrations. Put them back so the clock tree is not entirely orphaned. Fixes: 49fc825f0cc2 (clk: qcom: Consolidate common probe code) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Various fixes for MSM8960's global clock controllerKumar Gala2014-04-301-2/+2
| | | | | | | | | | | | | | | * Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs * Fix incorrect offset for PMIC_SSBI2_RESET * Fix typo: SIC_TIC -> SPS_TIC_H SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK * Fix naming convention: SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK SATA_SRC_CLK -> SATA_CLK_SRC Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Add basic support for APQ8064 global clock controller clocksKumar Gala2014-04-302-5/+29
| | | | | | | | | | | | | | The APQ8064 and MSM8960 share a significant amount of clock data and code between the two SoCs. Rather than duplicating the data we just add support for a unqiue APQ8064 clock table into the MSM8960 code. For now add just enough clocks to get a basic serial port going on an APQ8064 device. Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: trivial conflict due to missing ipq8064 support]
* clk: qcom: Consolidate common probe codeStephen Boyd2014-04-308-337/+196Star
| | | | | | | | | | Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix modular buildStephen Boyd2014-01-171-6/+6
| | | | | | | | | | According to Documentation/kbuild/makefiles.txt these symbols should be clk-qcom-y. Otherwise the build will fail if CONFIG_COMMON_CLK_QCOM=m. Fix it. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Add support for MSM8660's global clock controller (GCC)Stephen Boyd2014-01-163-0/+2828
| | | | | | | | | Add a driver for the global clock controller found on MSM8660 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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