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path: root/drivers/clk/renesas
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* clk: renesas: cpg-mssr: Add support to restore core clocks during resumeGeert Uytterhoeven2017-10-206-11/+23
| | | | | | | | | | | | | On R-Car Gen3 systems, PSCI system suspend powers down the SoC, possibly losing clock configuration. Hence add a notifier chain that can be used by core clocks to save/restore clock state during system suspend/resume. The implementation of the actual clock state save/restore operations is clock-specific, and to be registered with the notifier chain in the SoC or family-specific cpg_mssr_info.cpg_clk_register() callback. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: cpg-mssr: Restore module clocks during resumeGeert Uytterhoeven2017-10-201-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their clock register state is lost. Note that as the boot loader skips most initialization after system resume, clock register state differs from the state encountered during normal system boot, too. Hence after s2ram, some operations may fail because module clocks are disabled, while drivers expect them to be still enabled. E.g. EtherAVB fails when Wake-on-LAN has been enabled using "ethtool -s eth0 wol g": ravb e6800000.ethernet eth0: failed to switch device to config mode ravb e6800000.ethernet eth0: device will be stopped after h/w processes are done. ravb e6800000.ethernet eth0: failed to switch device to config PM: Device e6800000.ethernet failed to resume: error -110 In addition, some module clocks that were disabled by clk_disable_unused() may have been re-enabled, wasting power. To fix this, restore all bits of the SMSTPCR registers that represent clocks under control of Linux. Notes: - While this fixes EtherAVB operation after resume from s2ram, EtherAVB cannot be used as an actual wake-up source from s2ram, only from s2idle, due to PSCI limitations, - To avoid overhead on platforms not needing it, the suspend/resume code has a build time dependency on sleep and PSCI support, and a runtime dependency on PSCI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* clk: renesas: cpg-mssr: Add du1 clock to R8A7745Fabrizio Castro2017-10-201-0/+1
| | | | | | Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rz: clk-rz is meant for RZ/A1Geert Uytterhoeven2017-10-201-1/+1
| | | | | | | | | | The RZ family of Renesas SoCs has several different subfamilies (RZ/A, RZ/G, RZ/N, and RZ/T). Clarify that the renesas,rz-cpg-clocks DT bindings and clk-rz driver apply to RZ/A1 only. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Rob Herring <robh@kernel.org>
* clk: renesas: r8a77995: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+1
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017, the parent clock of the INTC-AP module clock on R-Car D3 is S1D2. This change has no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+1
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017, the parent clock of the INTC-AP module clock on R-Car M3-W is S0D3. This change has no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct parent clock of INTC-APGeert Uytterhoeven2017-10-161-1/+2
| | | | | | | | | | According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 8, 2017, the parent clock of the INTC-AP module clock on R-Car H3 ES2.0 is S0D3. This change has no functional impact. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen2: Delete error message for failed memory allocationMarkus Elfring2017-09-281-1/+0Star
| | | | | | | | | | | The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus fix affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: mstp: Delete error messages for failed memory allocationsMarkus Elfring2017-09-281-4/+1Star
| | | | | | | | | | | The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus fix affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add R8A77970 supportSergei Shtylyov2017-09-195-0/+212
| | | | | | | | | | | | | Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Daisuke Matsushita <daisuke.matsushita.ns@hitachi.com>. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Merge tag 'clk-renesas-for-v4.14-tag1' of ↵Stephen Boyd2017-08-2412-84/+560
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: * Add more module clocks for R-Car V2H and M3-W, * Add support for the R-Car Gen3 USB 2.0 clock selector PHY, * Add support for the new R-Car D3 SoC, * Allow compile-testing of all (sub)drivers now all dummy infrastructure is available, * Small fixes and cleanups. * tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add USB3.0 clock clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY clk: renesas: cpg-mssr: Add R8A77995 support clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 clk: renesas: Add r8a77995 CPG Core Clock Definitions clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table clk: renesas: rcar-gen3-cpg: Drop superfluous variable clk: renesas: Allow compile-testing of all (sub)drivers clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks clk: renesas: div6: Document fields used for parent selection
| * clk: renesas: r8a7796: Add USB3.0 clockHiromitsu Yamasaki2017-08-171-0/+1
| | | | | | | | | | | | | | | | | | This patch adds USB3.0-IF0 clock for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHYYoshihiro Shimoda2017-08-173-0/+194
| | | | | | | | | | | | | | | | | | | | R-Car USB 2.0 controller can change the clock source from an oscillator to an external clock via a register. So, this patch adds support the clock source selector as a clock driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven2017-08-165-0/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 CPG code. Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev. 0.55, Jun. 30, 2017. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
| * clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2017-08-162-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-164-37/+41
| | | | | | | | | | | | | | | | | | | | | | On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider value different from one. Extend struct rcar_gen3_cpg_pll_config to handle this. As all multipliers and dividers are small, table size increase can be kept limited by storing them in u8s instead of unsigned ints, which saves ca. 0.5 KiB for a generic kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang2017-07-191-26/+20Star
| | | | | | | | | | | | | | | | | | Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang2017-07-191-2/+1Star
| | | | | | | | | | | | | | 'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: Allow compile-testing of all (sub)driversGeert Uytterhoeven2017-07-171-19/+19
| | | | | | | | | | | | | | | | | | | | Enable compile-testing of the remaining clock drivers and subdrivers, now dummies are available for of_clk_get_from_provider(), of_device_compatible_match(), and rcar_rst_read_mode_pins(), and the CPG/MSSR driver core has been converted from of_match_node() to of_device_get_match_data(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocksGeert Uytterhoeven2017-07-171-0/+7
| | | | | | | | | | | | | | Add the module clocks for the Image Renderer Light (SRAM) Extended 3 (IMR-LX3/LSX3) Distortion Correction Engines on R-Car V2H. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: div6: Document fields used for parent selectionGeert Uytterhoeven2017-07-171-0/+3
| | | | | | | | | | | | | | | | | | Add the missing documentation for the fields in struct div6_clock related to parent selection for DIV6 clocks with selectable parents, as found in R/SH-Mobile SoCs. Fixes: c6d67fb037f4eaaf ("clk: shmobile: div6: support selectable-input clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: Convert to using %pOF instead of full_nameRob Herring2017-07-222-3/+2Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven2017-06-201-1/+1
| | | | | | | | | | | | | | If CONFIG_OF=n: drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’: drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union To fix this, use the of_device_get_match_data() helper, for which a dummy version is provided if CONFIG_OF=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: r8a7794: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-2/+266
| | | | | | | | | | | Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7792: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-2/+232
| | | | | | | | | | | Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-2/+302
| | | | | | | | | | | | Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7790: Add new CPG/MSSR driverGeert Uytterhoeven2017-05-245-1/+298
| | | | | | | | | | | Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven2017-05-243-36/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: renesas: cpg-mssr: Initialize error pointer using ERR_PTR()Geert Uytterhoeven2017-05-241-1/+1
| | | | | | | | | | | Coccinelle warns: drivers/clk/renesas/renesas-cpg-mssr.c:323:14-21: ERROR: PTR_ERR applied after initialization to constant on line 260 Initialize clk using ERR_PTR(-ENOTSUPP) instead of NULL to fix this. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Correct pwm, gpio, and i2c parent clocks on ES2.0Geert Uytterhoeven2017-05-151-13/+26
| | | | | | | | | | | | Cfr. the errata of April 14, 2017, for the R-Car Gen3 Hardware Manual Rev. 0.53E. These have no user-visible effect, as the clock frequencies stay the same. Fixes: 5573d194128b4733 ("clk: renesas: r8a7795: Add support for R-Car H3 ES2.0") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: Use pm_clk_no_clocks() helper i.s.o. direct accessGeert Uytterhoeven2017-05-152-2/+2
| | | | | | | | | | | | The pm_subsys_data.clock_list member exists only if CONFIG_PM_CLK=y. Hence direct accesses to this field break compile-testing on platforms where CONFIG_PM_CLK=n. To fix this, use the pm_clk_no_clocks() helper instead, for which a dummy version is provided if CONFIG_PM_CLK=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <simon.horman@netronome.com>
* clk: renesas: Do not build clk-div6 for R8A7792Geert Uytterhoeven2017-05-151-1/+1
| | | | | | | | R-Car V2H does not have "DIV6" programmable clocks, hence there is no need to build clk-div6.o. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
* clk: renesas: r8a7796: Add INTC-EX clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | | | | | | | Add the "intc-ex" clock to the R8A7796 CPG MSSR driver. According to information from the hardware team the INTC-EX parent clock is CP. The next data sheet version will include this information. [takeshi.kihara.df: Ported from commit f099aa075749 ("clk: shmobile: r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add PCIe clocksHarunobu Kurokawa2017-05-151-0/+2
| | | | | | | | | This patch adds PCIEC{0,1} clocks for R8A7796 SoC. Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add PWM clockRyo Kodama2017-05-151-0/+1
| | | | | | | | | | This patch adds PWM clock for PWM. Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Correct parent clock] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add HS-USB clockKazuya Mizuguchi2017-05-151-0/+1
| | | | | | | | | This patch adds HS-USB-IF clock for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add Sound DVC clocksKazuya Mizuguchi2017-05-151-0/+2
| | | | | | | | | This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add Sound SRC clockKazuya Mizuguchi2017-05-151-0/+13
| | | | | | | | | | | This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00, CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1) clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add Sound SSI clockKazuya Mizuguchi2017-05-151-0/+11
| | | | | | | | | | This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add USB-DMAC clocksHiromitsu Yamasaki2017-05-151-0/+2
| | | | | | | | | This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add Audio-DMAC clocksHiromitsu Yamasaki2017-05-151-0/+2
| | | | | | | | | | This patch adds A-DMAC{0,1} clocks for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Correct parent clocks, preserve sort order] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add EHCI/OHCI clocksKazuya Mizuguchi2017-05-151-0/+2
| | | | | | | | | This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC. Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7796: Add HDMI clockKoji Matsuoka2017-05-151-0/+2
| | | | | | | | | This patch adds HDMI-IF0 clock for R8A7796 SoC. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add HS-USB ch3 clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add USB-DMAC ch3 clockTakeshi Kihara2017-05-151-0/+2
| | | | | | | | | This patch supports the clock of USB-DMAC ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7795: Add EHCI/OHCI ch3 clockTakeshi Kihara2017-05-151-0/+1
| | | | | | | | | This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795 ES2.0 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7745: Remove PLL configs for MD19=0Geert Uytterhoeven2017-05-151-11/+2Star
| | | | | | | | | | | According to tables 7.5b and 7.6b of the RZ/G Series Hardware User's Manual Rev.1.00, MD19=0 is a prohibited setting. Hence stop looking at MD19, and remove all PLL configurations for MD19=0. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7745: Remove nonexisting scu-src[0789] clocksGeert Uytterhoeven2017-05-151-4/+0Star
| | | | | | | RZ/G1E does not have the SCU-SRC[0789] modules and module clocks. Fixes: 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2Geert Uytterhoeven2017-05-151-4/+19
| | | | | | | | | | | | | | | R-Car V2H and E2 do not have the PLL0CR register, but use a fixed multiplier (depending on mode pins) and divider. This corrects the clock rate of "pll0" (PLL0 VCO after post divider) on R-Car V2H and E2 from 1.5 GHz to 1 GHz. Inspired by Sergei Shtylyov's work for the common R-Car Gen2 and RZ/G Clock Pulse Generator support core. Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Fixes: 0dce5454d5c25858 ("ARM: shmobile: Initial r8a7794 SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0Geert Uytterhoeven2017-03-301-11/+27
| | | | | | | | | | | | Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28. Add support for that, but retain the old behavior for R-Car H3 ES1.x and M3-W ES1.0 using a quirk. Inspired by a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-19 22:26:39 +0200