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path: root/drivers/clk/samsung/clk-exynos5433.c
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* clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspendMarek Szyprowski2018-10-051-0/+2
| | | | | | | | All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume cycle, otherwise TM2(e) boards hangs before entering the suspend mode. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUsMarek Szyprowski2018-10-051-0/+29
| | | | | | | | | | | | Before entering system suspend, one has to ensure that some clocks from TOP, CPIF and PERIC CMUs are enabled. This is needed by the firmware to properly perform system suspend operation. Instead of adding more and more clocks with CRITICAL flag, simply enable those clocks directly in respective CMU registers using 'suspend_regs' feature. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resumeMarek Szyprowski2018-10-051-1/+1
| | | | | | | | | | | | | | | SoC clock drivers should suspend after every other drivers in the system, which are using clocks and resume before them. The last stage for calling suspend device callbacks is NOIRQ stage and there exists driver, which use that state (dwmmc-exynos), so Exynos5433 clocks driver should also use it. During the same stage, clocks driver will be always suspended after its clients as a direct result of proper device probe order (deferred probe reorders the suspend call sequence). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
* treewide: Use struct_size() for devm_kmalloc() and friendsKees Cook2018-06-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replaces open-coded struct size calculations with struct_size() for devm_*, f2fs_*, and sock_* allocations. Automatically generated (and manually adjusted) from the following Coccinelle script: // Direct reference to struct field. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(*VAR->ELEMENT), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // mr = kzalloc(sizeof(*mr) + m * sizeof(mr->map[0]), GFP_KERNEL); @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; identifier VAR, ELEMENT; expression COUNT; @@ - alloc(HANDLE, sizeof(*VAR) + COUNT * sizeof(VAR->ELEMENT[0]), GFP) + alloc(HANDLE, struct_size(VAR, ELEMENT, COUNT), GFP) // Same pattern, but can't trivially locate the trailing element name, // or variable name. @@ identifier alloc =~ "devm_kmalloc|devm_kzalloc|sock_kmalloc|f2fs_kmalloc|f2fs_kzalloc"; expression HANDLE; expression GFP; expression SOMETHING, COUNT, ELEMENT; @@ - alloc(HANDLE, sizeof(SOMETHING) + COUNT * sizeof(ELEMENT), GFP) + alloc(HANDLE, CHECKME_struct_size(&SOMETHING, ELEMENT, COUNT), GFP) Signed-off-by: Kees Cook <keescook@chromium.org>
* clk: samsung: Add compile time PLL rate validatorsAndrzej Hajda2018-02-231-58/+58
| | | | | | | | | | | | | | | | | | | | Rates declared in PLL rate tables should match exactly rates calculated from PLL coefficients. To avoid possible mistakes we can use compile time validation. The patch introduces such validators and expands all initializers with additional input frequency parameter, required to validate rates. Since S3C24xx PLLs requires different validators two new macros have been introduced to deal with it. Also, since PLLs 4502 and 4508 have different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE. As the patch adds only compile time validators it should not have impact on compiled code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Fix PLL ratesAndrzej Hajda2018-02-231-6/+6
| | | | | | | | | | | | | | | | | | | | Rates declared in PLL rate tables should match exactly rates calculated from the PLL coefficients. If that is not the case, rate of the PLL's child clock might be set not as expected. For instance, if in the PLL rates table we have a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate will return 393216003. If we now attempt to set rate of a PLL's child divider clock to 393216000/2 its rate will be 131072001, rather than 196608000. That is, the divider will be set to 3 instead of 2, because 393216003/2 is greater than 196608000. To fix this issue declared rates are changed to exactly match rates generated by the PLL, as calculated from the P, M, S, K coefficients. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Extend list of available AUD_PLL output frequenciesSylwester Nawrocki2018-02-141-0/+1
| | | | | | | | | Add one more entry to the exynos5433_aud_pll_rates table, this allows to support audio sample rates: 48000, 96000, 192000 Hz with minimum error. The M, P, S, K values re confirmed by the HW team. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
* clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclkSylwester Nawrocki2018-02-141-1/+1
| | | | | | | | | The sclk_ioclk_i2s1_bclk clock is not currently handled by any driver and disabling this clock by the clk core prevents proper operation of the I2S1 block. CLK_IGNORE_UNUSED flag is added as a temporary fix. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
* clk: samsung: Remove redundant dev_err call in exynos5433_cmu_probe()Wei Yongjun2018-02-141-3/+1Star
| | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: mark PM functions as __maybe_unusedArnd Bergmann2017-10-111-2/+2
| | | | | | | | | | | | | | | | | The suspend/resume functions are referenced conditionally, causing a harmless warning when CONFIG_PM is disabled: drivers/clk/samsung/clk-exynos5433.c:5476:12: error: 'exynos5433_cmu_resume' defined but not used [-Werror=unused-function] drivers/clk/samsung/clk-exynos5433.c:5453:12: error: 'exynos5433_cmu_suspend' defined but not used [-Werror=unused-function] This marks both as __maybe_unused to shut up the warning. Fixes: 523d3de41f02 ("clk: samsung: exynos5433: Add support for runtime PM") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add support for runtime PMMarek Szyprowski2017-09-081-85/+324
| | | | | | | | | | | | | | | | | | | | | | Add runtime pm support for all clock controller units (CMU), which belong to power domains and require special handling during on/off operations. Typically special values has to be written to MUX registers to change internal clocks parents to OSC clock before turning power off. During such operation all clocks, which enter CMU has to be enabled to let MUX to stabilize. Also for each CMU there is one special parent clock, which has to be enabled all the time when any access to CMU registers is being done. This patch solves most of the mysterious external abort and freeze issues caused by a lack of proper parent CMU clock enabled or incorrect turn off procedure. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1503302703-13801-4-git-send-email-m.szyprowski@samsung.com
* Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd2017-01-271-16/+20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY - Exynos PLL code updates and overall minor clean-ups * tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung: clk: samsung: mark s3c...._clk_sleep_init() as __init clk: samsung: Add enable/disable support for PLL35XX clocks clk: samsung: exynos5433: Correct typos in SoC name clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
| * clk: samsung: exynos5433: Correct typos in SoC nameMarek Szyprowski2017-01-271-14/+14
| | | | | | | | | | | | | | | | | | | | This patch fixes simple typos in Exynos5433 clocks driver. The SoC name was referred a few times as '5443' instead of '5433'. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL ratesMarek Szyprowski2017-01-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clock-*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski2017-01-271-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as criticalChanwoo Choi2016-12-291-4/+4
|/ | | | | | | | | | | | | | | The ACLK_BUS0/1/2 are used for NoC (Network on Chip). If NoC's clocks are disabled, the system halt happens. Following clocks must be always enabled: - CLK_ACLK_BUS0_400 : NoC's bus clock for PERIC/PERIS/FSYS/MSCL, - CLK_ACLK_BUS1_400 : NoC's bus clock for MFC/HEVC/G3D, - CLK_ACLK_BUS2_400 : NoC's bus clock for GSCL/DISP/G2D/CAM0/CAM1/ISP. This patch also adds the CLK_SET_RATE_PARENT flag to the CLK_SCLK_JPEG_MSCL because this clock should be used for bus frequency scaling. This clock need to be changed on the fly with CLK_SET_RATE_PARENT flag. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Mark some clocks as criticalMarek Szyprowski2016-11-181-14/+14
| | | | | | | | | | | | | | Some parent clocks of the Exynos5433 CMUs must be always enabled to access any register in the given CMU or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused) to prevent disabling them. Reported-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Fix parent clocks for FSYS blockMarek Szyprowski2016-11-171-1/+1
| | | | | | | | | The proper parent clock for FSYS block is "aclk_fsys_200" according to the Exynos5433 reference manual. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocksAndi Shyti2016-07-131-3/+2Star
| | | | | | | | | | | | | | | | | Because the Exynos5433 SPI driver supports the ioclk handling and the following patch: http://marc.info/?l=linux-kernel&m=146787645626318&w=2 fixes a synchronus abort issue, none of the SPI clocks require any critical handling: remove, then, the CLK_IGNORE_UNUSED flag for the SPI related clocks. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1468317736-18841-8-git-send-email-andi.shyti@samsung.com
* clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag to PCIE deviceJaehoon Chung2016-06-101-5/+6
| | | | | | | | | | | This patch adds the CLK_IGNORE_UNUSED flag for PCI Express's clocks which need to remain enabled. The 'pcie' gate clock definition is also added. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flags to avoid hang during S2RJonghwa Lee2016-06-101-12/+22
| | | | | | | | | | Some clocks are required to be unmasked during suspend to RAM. Otherwise the PMU will stuck and the power down sequence will never be completed. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add CLK_IGNORE_UNUSED flag for AUD UARTBeomho Seo2016-06-101-1/+1
| | | | | | | | | | This patch adds CLK_IGNORE_UNUSED flag for sclk_aud_uart gate clock for uart3 operation. Signed-off-by: Beomho Seo <beomho.seo@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [s.nawrocki@samsung.com: edited the patch's summary] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: add CPU clocks configuration data and instantiate ↵Bartlomiej Zolnierkiewicz2016-06-021-8/+64
| | | | | | | | | | | | CPU clocks Add the CPU clocks configuration data and instantiate the CPU clocks type for Exynos5433. Cc: Kukjin Kim <kgene@kernel.org> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: prepare for adding CPU clocksBartlomiej Zolnierkiewicz2016-06-021-30/+55
| | | | | | | | | | | | | Open-code samsung_cmu_register_one() calls for CMU_APOLLO and CMU_ATLAS setup code as a preparation for adding CPU clocks support for Exynos5433. There should be no functional change resulting from this patch. Cc: Kukjin Kim <kgene@kernel.org> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Move PLL rates data to init sectionKrzysztof Kozlowski2016-06-021-2/+2
| | | | | | | | | The arrays with initialization data of PLLs can be moved to initconst section because they are referenced only from other initconst-level symbols. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Constify all clock initializersKrzysztof Kozlowski2016-06-021-120/+120
| | | | | | | All of initialization data can be made const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Remove CLK_IS_ROOTStephen Boyd2016-03-031-40/+34Star
| | | | | | | This flag is a no-op now. Remove usage of the flag. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocksJonghwa Lee2016-02-251-2/+2
| | | | | | | | This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2} clocks definition. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definitionSylwester Nawrocki2016-02-251-2/+2
| | | | | | | Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Drop RO registers from the save/restore listsSylwester Nawrocki2016-02-251-100/+0Star
| | | | | | | Restoring read-only registers is of not much effect, drop them from the respective lists. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocksMarek Szyprowski2016-02-251-2/+2
| | | | | | | | This fixes bit field offsets in the CMU_TOP CLK_DIV_SCLK_ISP_SENSOR_{A,B} clock definitions. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocksSylwester Nawrocki2016-02-251-6/+6
| | | | | | | This corrects assignment of bit offsets of the MUX_SEL_CAM04 register to the respective mux clocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock namesSylwester Nawrocki2016-02-231-3/+3
| | | | | | This fixes "MPWM" -> "WPWM" typo in 3 *ISP_MWPM clock definitions. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk/samsung: exynos5433: add pclk_decon clockAndrzej Hajda2016-02-031-0/+2
| | | | | | | This undocumented gate clock is used by DECON IP. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk/samsung: exynos5433: add definitions of HDMI-PHY output clocksAndrzej Hajda2016-02-031-2/+4
| | | | | | | | | HDMI driver must re-parent respective muxes during HDMI-PHY on/off to HDMI-PHY output clocks. To reference those clocks their definitions should be added. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: Properly include clk.h and clkdev.hStephen Boyd2015-07-201-2/+0Star
| | | | | | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include clk.h in files that are using it. The clkdev.h header isn't always used either, so remove it and add in slab.h where files were relying on it to include slab for them. Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: exynos5433: Add CLK_IGNORE_UNUSED flag to clocks for SMCJonghwa Lee2015-06-101-18/+18
| | | | | | | | | | This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for operation of secure monitor call (smc). System will hang when it executes 'smc' with one of those clock is gated. All related clocks must be enabled. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Add clock flag to support the DVFS of GPUJoonyoung Shim2015-06-101-9/+9
| | | | | | | | | | | | | This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to 'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR of the MALI device. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> [cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk] Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Add DIV_CPIF to the list of stored registers on suspendHyungwon Hwang2015-06-101-0/+1
| | | | | | | | | | This DIV_CPIF register must be stored when the system is suspended, and must be restored on system resume. This patch adds the register to the list of restored registers. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Add CLK_SET_RATE_PARENT to support DVFS for big.LITTLE coreChanwoo Choi2015-06-101-14/+12Star
| | | | | | | | | | | This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57} core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Fix wrong PMS value of exynos5433_pll_ratesChanwoo Choi2015-04-291-3/+3
| | | | | | | | | | | This patch fixes the wrong PMS value of exynos5433_pll_rates table for {ATLAS|APOLLO|MEM0|MEM1|BUS|MFC|MPHY|G3D|DISP|ISP|_PLL. - 720 MHz (mdiv=360, pdiv=6, sdiv=1) -> 700 MHz (mdiv=175, pdiv=3, sdiv=1) - 350 MHz (mdiv=360, pdiv=6, sdiv=2) -> (mdiv=350, pdiv=6, sdiv=2) - 133 MHz (mdiv=552, pdiv=6, sdiv=4) -> (mdiv=532, pdiv=6, sdiv=4) Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Fix wrong parent clock of sclk_apollo clockChanwoo Choi2015-04-291-1/+1
| | | | | | | | | This patch fixes the wrong parent clock of sclk_apollo clock from 'div_apollo_pll' to 'div_apollo2'. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT clk register assignmentJonghwa Lee2015-04-291-1/+1
| | | | | | | | | | CLK_PCLK_MONOTONIC_CNT clock had a wrong register assigned to it. The correct register is ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT. Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEGJonghwa Lee2015-04-291-1/+1
| | | | | | | | | | | This patch fixes the wrong offoset of PCLK_MSCL_SECURE_SMMU_JPEG in CMU_MSCL domain. Fixes: b274bbfd8b4a94 (clk: samsung: exynos5433: Add clocks for CMU_MSCL domain) Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Move CLK_SCLK_HDMI_SPDIF_DISP clock to CMU_TOP domainChanwoo Choi2015-02-051-5/+5
| | | | | | | | | | This patch fixes the bug of CLK_SCLK_HDMI_SPDIF_DISP clock because this clock should be included in CMU_TOP domain. So, this patch moves the CLK_SCLK_HDMI_ SPDIF_DISP clock from CMU_MIF to CMU_TOP domain. Reported-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add clocks for CMU_CAM1 domainChanwoo Choi2015-02-051-0/+435
| | | | | | | | | This patch adds the mux/divider/gate clocks for CMU_CAM1 domain which generates the clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add clocks for CMU_CAM0 domainChanwoo Choi2015-02-051-0/+501
| | | | | | | | | This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add clocks for CMU_ISP domainChanwoo Choi2015-02-051-0/+267
| | | | | | | | | This patch adds the mux/divider/gate clocks for CMU_ISP domain which generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add clocks for CMU_HEVC domainChanwoo Choi2015-02-051-0/+115
| | | | | | | | | This patch adds the mux/divider/gate clocks for CMU_HEVC domain which generates the clocks for HEVC(High Efficiency Video Codec) decoder IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* clk: samsung: exynos5433: Add clocks for CMU_MFC domainChanwoo Choi2015-02-051-0/+113
| | | | | | | | | This patch adds the mux/divider/gate clocks for CMU_MFC domain which generates the clocks for MFC(Multi-Format Codec) IP. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-13 18:33:18 +0200