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| * clk: sunxi: Support factor clocks with N factor starting not from 0Chen-Yu Tsai2014-07-042-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a N multiplier factor that starts from 1, not 0. This patch adds an option to the factor clk driver's config data structures to specify the base value of N. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai2014-07-041-5/+3Star
| | | | | | | | | | | | | | | | | | | | | | With sunxi_gates clocks registered with clkdev, we can use the protected clocks list to enable the "ahb_sdram" clock, instead of looking for it and adding CLK_IGNORE_UNUSED inline in the clock setup code. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: register clock gates with clkdevChen-Yu Tsai2014-07-041-0/+1
| | | | | | | | | | | | | | | | | | | | The new important clock protect code requires the clocks be registered with clkdev. This was missing for sunxi_gates type clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: sunxi: fix devm_ioremap_resource error detection codeHimangi Saraogi2014-07-021-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | devm_ioremap_resource returns an ERR_PTR value, not NULL, on failure. A simplified version of the semantic match that finds this problem is as follows: // <smpl> @@ expression e,e1; statement S; @@ *e = devm_ioremap_resource(...); if (!e1) S // </smpl> Signed-off-by: Himangi Saraogi <himangi774@gmail.com> Acked-by: Julia Lawall <julia.lawall@lip6.fr> Acked-by Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: add PRCM (Power/Reset/Clock Management) clks supportBoris BREZILLON2014-06-114-0/+411
| | | | | | | | | | | | | | | | The PRCM (Power/Reset/Clock Management) unit provides several clock devices: - AR100 clk: used to clock the Power Management co-processor - AHB0 clk: used to clock the AHB0 bus - APB0 clk and gates: used to clk peripherals connected to the APB0 bus Add support for these clks in a separate driver so that they can be probed as platform devices instead of registered during early init. This is needed to be able to probe PRCM MFD subdevices. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sun6i: Protect SDRAM gating bitMaxime Ripard2014-06-111-0/+1
| | | | | | | | | Prevent the SDRAM controller from being gated by force-enabling it in the machine code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sun6i: Protect CPU clockMaxime Ripard2014-06-111-0/+1
| | | | | | | | | | | | Right now, AHB is an indirect child clock of the CPU clock. If that happens to change, since the CPU clock has no other consumers declared in Linux, it would be shut down, which is not really a good idea. Prevent this by forcing it enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Rework clock protection codeMaxime Ripard2014-06-111-28/+44
| | | | | | | | | | | | Since we start to have a lot of clocks to protect, some of them in a few SoCs only, it becomes difficult to handle the clock protection without having to add per machine exceptions. Add per-SoC data to tell which clock to leave enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard2014-06-113-99/+121
| | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The gmac clock is pretty easy to deal with, since it's pretty much isolated and doesn't have any dependency on the other clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard2014-06-113-57/+74
| | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The main oscillator is pretty easy to deal with, since it's pretty much isolated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Remove calls to clk_putMaxime Ripard2014-06-111-6/+2Star
| | | | | | | | | | | Callers of clk_put must disable the clock first. This also means that as long as the clock is enabled the driver should hold a reference to that clock. Hence, the call to clk_put here are bogus and should be removed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Implement A31 USB clockMaxime Ripard2014-06-111-0/+6
| | | | | | | | | | | The A31 USB clock slightly differ from its older counterparts, mostly because it has a different gate for each PHY, while the older one had a single gate for all the phy. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* Merge tag 'clk-for-linus-3.16' of ↵Linus Torvalds2014-06-082-0/+73
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux into next Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.16 are pretty typical: mostly clock driver additions and fixes. There are additions to the clock core code for some of the basic types (e.g. the common divider type has some fixes and featured added to it). One minor annoyance is a last-minute dependency that wasn't handled quite right. Commit ba0fae3b06a6 ("clk: berlin: add core clock driver for BG2/BG2CD") in this pull request depends on include/dt-bindings/clock/berlin2.h, which is already in your tree via the arm-soc pull request. Building for the berlin platform will break when the clk tree is built on it's own, but merged into your master branch everything should be fine" * tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits) mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs clk: export __clk_round_rate for providers clk: versatile: free icst on error return clk: qcom: Return error pointers for unimplemented clocks clk: qcom: Support msm8974pro global clock control hardware clk: qcom: Properly support display clocks on msm8974 clk: qcom: Support display RCG clocks clk: qcom: Return highest rate when round_rate() exceeds plan clk: qcom: Fix mmcc-8974's PLL configurations clk: qcom: Fix clk_rcg2_is_enabled() check clk: berlin: add core clock driver for BG2Q clk: berlin: add core clock driver for BG2/BG2CD clk: berlin: add driver for BG2x complex divider cells clk: berlin: add driver for BG2x simple PLLs clk: berlin: add driver for BG2x audio/video PLL clk: st: Terminate of match table clk/exynos4: Fix compilation warning ARM: shmobile: r8a7779: Add clock index macros for DT sources clk: divider: Fix overflow in clk_divider_bestdiv clk: u300: Terminate of match table ...
| * clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede2014-05-151-1/+2
| | | | | | | | | | | | | | | | __clk_get_hw is supposed to be used by clk providers, not clk consumers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: Implement MMC phase controlEmilio López2014-05-061-0/+36
| | | | | | | | | | | | | | | | HdG: add header exporting clk_sunxi_mmc_phase_control Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: factors: automatic reparenting supportEmilio López2014-05-061-0/+36
| | | | | | | | | | | | | | | | | | | | This commit implements .determine_rate, so that our factor clocks can be reparented when needed. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: sunxi: fix function type for CLK_OF_DECLARERob Herring2014-05-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Adding function type checking to CLK_OF_DECLARE found a type mismatch with sunxi_init_clocks. The function takes a single struct device_node parameter. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: sunxi: avoid double DT matchingRob Herring2014-05-201-2/+1Star
|/ | | | | | | | | | | | | | Use for_each_matching_node_and_match instead of for_each_matching_node plus of_match_node to avoid searching the DT twice for each node. The sunxi DT scanning code should really be re-worked rather than have its own private matching infrastructure. It is working around needing a function pointer and a data pointer for each compatible match. Signed-off-by: Rob Herring <robh@kernel.org> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
* clk: sunxi: fix thinko in commentEmilio López2014-03-191-1/+1
| | | | | | | | This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: fix some calculationsEmilio López2014-03-191-3/+3
| | | | | | | | | | Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: fix A20 PLL4 calculationEmilio López2014-03-191-0/+7
| | | | | | | | | Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Add new clock compatiblesMaxime Ripard2014-02-181-15/+15
| | | | | | | | | | The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the clock driver for consistency, and keep the older one for backward compatibility. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai2014-02-181-0/+96
| | | | | | | | | | The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add support for PLL6 on the A31Maxime Ripard2014-02-181-0/+45
| | | | | | | | The A31 has a slightly different PLL6 clock. Add support for this new clock in our driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add USB clock register defintionsRoman Byshko2014-02-181-0/+12
| | | | | | | | | | Add register definitions for the usb-clk register found on sun4i, sun5i and sun7i SoCs. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add support for USB clock-register reset bitsHans de Goede2014-02-181-0/+71
| | | | | | | | | | | The usb-clk register is special in that it not only contains clk gate bits, but also has a few reset bits. This commit adds support for this by allowing gates type sunxi clks to also register a reset controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai2014-02-031-1/+2
| | | | | | | | | | | Divs clocks consist of a parent factor clock with multiple outputs, and seperate clocks for each output. Get the name of the parent clock from the parent factor clock, instead of the DT node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai2014-02-031-9/+18
| | | | | | | | | | | Some factor clocks, such as the parent clock of pll5 and pll6, have multiple output names. Add the corresponding names to factors_data tied to compatible string. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai2014-02-031-0/+6
| | | | | | | | | | | | sunxi clock drivers use dt node name as clock name, but clock nodes should be named clk@X, so the names would be the same. Let the drivers read clock names from dt clock-output-names property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: fix overflow when setting up divided factorsEmilio López2014-01-271-1/+1
| | | | | | | | | | | Currently, we are allocating space for two pointers, when we actually may need to store three of them (two divisors plus the original clock). Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl happy. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai2013-12-281-0/+57
| | | | | | | | | This patch adds support for the external clock outputs on the Allwinner A20 SoC. The clock outputs are similar to "module 0" type clocks, with different offsets and widths for clock factors. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: support better factor DT nodesEmilio López2013-12-281-0/+9
| | | | | | | | | | | | | | | | | | | | | The DT nodes should look like abc_clk: clk@deadbeef { ... clock-output-names = "abc"; } But our old DT nodes look like abc: abc@deadbeef { ... } So, let's support both formats, until we can transition everything to the new, correct one. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: mod0 supportEmilio López2013-12-281-0/+57
| | | | | | | | This commit implements support for the "module 0" type of clocks, as used by MMC, IR, NAND, SATA and other components. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: add PLL5 and PLL6 supportEmilio López2013-12-281-0/+230
| | | | | | | | This commit implements PLL5 and PLL6 support on the sunxi clock driver. These PLLs use a similar factor clock, but differ on their outputs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: make factors_clk_setup return the clock it registersEmilio López2013-12-281-7/+8
| | | | | | | | We will be needing this to register a factor clock as parent with leaf divisors on a single call. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: add gating support to PLL1Emilio López2013-12-281-0/+2
| | | | | | | | | This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: clean the magic number of mux parentsEmilio López2013-12-281-2/+3
| | | | | | | | This was pointed out during the review of the factor patches. Let's indicate what does that magic 5 mean. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: register factors clocks behind compositeEmilio López2013-12-283-73/+76
| | | | | | | | | | This commit reworks factors clock registration to be done behind a composite clock. This allows us to additionally add a gate, mux or divisors, as it will be needed by some future PLLs. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into ↵Mike Turquette2013-12-012-14/+48
|\ | | | | | | | | | | | | | | | | | | | | | | clk-next-sunxi-rebase Allwinner sunXi SoCs clock changes Those are mostly random fixes, except for one patch to the composite clock that adds support for automatic reparenting. Conflicts: drivers/clk/sunxi/clk-sunxi.c
| * drivers: clk: sunxi: Fix memory leakage in clk-sunxi.cVictor N. Ramos Mello2013-11-101-11/+17
| | | | | | | | | | | | | | | | Fix a possible memory leak in sun4i_osc_clk_setup(). Moved clock-frequency check to save superfluous allocation. Signed-off-by: Victor N. Ramos Mello <victornrm@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: protect core clocks from accidental shutdownEmilio López2013-11-101-0/+28
| | | | | | | | | | | | | | | | | | | | Some important clocks may get disabled as a side effect of another clock being disabled, because they have no consumers. This patch implements a mechanism so those clocks can be claimed by the driver and therefore remain enabled at all times. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: factors: clear variables before using themEmilio López2013-11-101-1/+1
| | | | | | | | | | | | | | Random bits may get into our factors if we don't clear n, k, m and p. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: factors: fix off-by-one masksEmilio López2013-11-101-1/+1
| | | | | | | | | | | | | | | | | | The previous code would generate one bit too long masks, and was needlessly complicated. This patch replaces it by simpler code that can generate the masks correctly. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | clk: sunxi: declare OF clock providerSebastian Hesselbarth2013-09-291-5/+6
|/ | | | | | | | | | | | Common clock framework allows to register clock providers to get called on of_clk_init() by using CLK_OF_DECLARE. This converts sunxi clock providers to make use of it and get rid of the mach specific clk init call. As sunxi has a bunch of independent clk provider nodes, we hook current clock init to board compatible to make it called once. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Fix incorrect placement of __initconstSachin Kamat2013-08-281-30/+30
| | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: refreshed patch based on sunxi changes]
* clk: sunxi: Add Allwinner A20 gatesMaxime Ripard2013-08-261-0/+15
| | | | | | | | | | | The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Add A31 clocks supportMaxime Ripard2013-08-261-0/+124
| | | | | | | | | | | The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Allow to specify the divider width from the dividers dataMaxime Ripard2013-08-261-11/+13
| | | | | | | | | The divider width used to be hardcoded. Some A31 dividers are no longer with the hardcoded width, so we need to make it specific to each divider and set it in the dividers data. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Rename the structure to prepare the addition of sun6iMaxime Ripard2013-08-261-27/+27
| | | | | | | | Rename all the generic-named structure to sun4i to avoid confusion when we will introduce the sun6i (A31) clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: fix initialization of basic clocksEmilio López2013-08-261-8/+3Star
| | | | | | | | | | | | With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-10-14 12:55:26 +0200