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* Merge tag 'clk-for-linus-4.2' of ↵Linus Torvalds2015-07-025-9/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clock framework updates from Michael Turquette: "The changes to the common clock framework for 4.2 are dominated by new drivers and updates to existing ones, as usual. There are some fixes to the framework itself and several cleanups for sparse warnings, etc" * tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits) clk: stm32: Add clock driver for STM32F4[23]xxx devices dt-bindings: Document the STM32F4 clock bindings cpufreq: exynos: remove Exynos4210 specific cpufreq driver support ARM: Exynos: switch to using generic cpufreq driver for Exynos4210 clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock clk: samsung: add infrastructure to register cpu clocks clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support doc: dt: add documentation for lpc1850-ccu clk driver clk: add lpc18xx ccu clk driver doc: dt: add documentation for lpc1850-cgu clk driver clk: add lpc18xx cgu clk driver clk: keystone: add support for post divider register for main pll clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED clk: cygnus: remove Cygnus dummy clock binding clk: cygnus: add clock support for Broadcom Cygnus clk: Change bcm clocks build dependency clk: iproc: add initial common clock support clk: iproc: define Broadcom iProc clock binding MAINTAINERS: update email for Michael Turquette clk: meson: add some error handling in meson_clk_register_cpu() ...
| * clk: ti: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2015-06-041-1/+1
| | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: ti: Silence sparse warningsStephen Boyd2015-05-154-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/clk/ti/clk.c:125:31: warning: incorrect type in return expression (different address spaces) drivers/clk/ti/clk.c:125:31: expected void [noderef] <asn:2>* drivers/clk/ti/clk.c:125:31: got void * drivers/clk/ti/clk.c:132:31: warning: incorrect type in return expression (different address spaces) drivers/clk/ti/clk.c:132:31: expected void [noderef] <asn:2>* drivers/clk/ti/clk.c:132:31: got void * drivers/clk/ti/dpll.c:180:14: warning: symbol '_get_reg' was not declared. Should it be static? drivers/clk/ti/fapll.c:624:32: warning: Using plain integer as NULL pointer drivers/clk/ti/fapll.c:625:31: warning: Using plain integer as NULL pointer drivers/clk/ti/fapll.c:630:40: warning: Using plain integer as NULL pointer drivers/clk/ti/clk-dra7-atl.c:158:22: warning: symbol 'atl_clk_ops' was not declared. Should it be static? drivers/clk/ti/clk-dra7-atl.c:170:39: warning: Using plain integer as NULL pointer Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: ti: dra7-atl-clock: Fix possible ERR_PTR dereferenceKrzysztof Kozlowski2015-05-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | of_clk_get_from_provider() returns ERR_PTR on failure. The dra7-atl-clock driver was not checking its return value and immediately used it in __clk_get_hw(). __clk_get_hw() dereferences supplied clock, if it is not NULL, so in that case it would dereference an ERR_PTR. Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | CLK: TI: always enable DESHDCP clockTomi Valkeinen2015-06-041-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DESHDCP clock is needed on DRA7 based SoCs to enable the DSS IP. That clock is an odd one, as it is not supposed to be any kind of core clock for DSS, and we don't even support HDCP, but the clock is still needed even for the HWMOD framework to be able to reset the DSS IP. As there's no support for multiple core clocks in the HWMOD framework, we don't have any obvious place to enable this clock when DSS IP is being enabled. Furthermore, the HDMI on OMAP5 DSS is the same as on DRA7, and OMAP5 does not have any such clock configuration bit. This suggests that on OMAP5 the DESHDCP clock is always enabled, and for DRA7 we have the possibility to gate it. So, as we don't have any clean way to enable and disable the clock based on the need, this patch enables the clock at boot time, making it work similarly to OMAP5. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Michael Turquette <mturquette@linaro.org>
* | arm: dra7: add DESHDCP clockTomi Valkeinen2015-06-031-0/+1
|/ | | | | | | Add a new Linux clock for DRA7 based SoCs to control DESHDCP clock. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com>
* clk: don't use __initconst for non-const arraysUwe Kleine-König2015-04-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: constify of_device_id arrayFabian Frederick2015-04-012-2/+2
| | | | | | | | | | | of_device_id is always used as const. (See driver.of_match_table and open firmware functions) __initdata updated to __initconst for static const struct of_device_id ti_clkdm_match_table[] Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'for-4.1-clk-ti' of github.com:t-kristo/linux-pm into clk-nextMichael Turquette2015-03-2514-72/+318
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| * clk: ti: Implement FAPLL set_rate for the PLLTony Lindgren2015-03-241-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have a fractional divider for the synthesizer, just implement a simple multiply logic for the PLL. It seems the PLL divider needs to have also the multiplier set for the PLL to lock. At least I have not yet figured out if divided rates are doable. So let's just ignore the PLL divider for now as the synthesizer has both integer and fractional dividers so we don't even need to use the PLL divider for the rates we know work with PLL locking. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: Implement FAPLL set_rate for the synthesizerTony Lindgren2015-03-241-2/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We can pretty much get any rate out of the FAPLL because of the fractional divider. Let's first try just adjusting the post divider, and if that is not enough, then reprogram both the fractional divider and the post divider. Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: Fix FAPLL recalc_rate for rounding errorsTony Lindgren2015-03-241-6/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to round the calculated value to have it match the requested rate. While at it, let's fix a typo and use a define for SYNTH_MAX_DIV_M as we will need it in later patches for set_rate. And let's remove two unused includes. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: DRA7: Add timer_sys_ck aliases for Timers 13 through 16Suman Anna2015-03-241-0/+4
| | | | | | | | | | | | | | | | | | | | The OMAP DMTimer API, omap_dm_timer_set_source(), uses the clock name timer_sys_ck for setting a timer's clock source for the source index OMAP_TIMER_SRC_SYS_CLK. There is currently no clock alias data for the Timers 13 through 16 for this clock name, so add the same. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: DRA7: Correct timer_sys_ck clock aliases for TimersSuman Anna2015-03-241-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent of a timer node using 3 different values that use fixed parent names for the clocks. The parent name, timer_sys_ck, is used for setting the parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock input. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: OMAP5: Correct the DT clock aliases for timersSuman Anna2015-03-241-11/+11
| | | | | | | | | | | | | | | | | | | | | | The DT clock aliases for Timers use the legacy (non-DT) device names and a source clock named sys_ck. OMAP5 is DT-boot only, so correct the DT clock aliases to use the DT device names instead. Also, the source clock name is corrected from 'sys_ck' to 'timer_sys_ck', the name used by the OMAP dmtimer driver. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: OMAP4: Remove the legacy timer DT clock aliasesSuman Anna2015-03-241-11/+0Star
| | | | | | | | | | | | | | | | | | | | The DT clock aliases for timers using the legacy OMAP timer device names have been cleaned up. These device names reflect the names used in legacy boot, and are no longer applicable as OMAP4 is DT boot only now. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: clk-3xxx-legacy: Correct McBSP related clock aliasesPeter Ujfalusi2015-03-241-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2). Add missing mcbsp clock aliases. Collect the McBSP clock definition in one location at the same time. Fixes the following warning on boot: [ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16 [ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: clk-3xxx: Correct McBSP related DT clock definitionsPeter Ujfalusi2015-03-241-12/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | In DT boot we do not have devices named as omap-mcbsp.X. Correct the McBSP2/4 ick mapping (they were 2->4 and 4->2). Collect the McBSP clock definition in one location at the same time. Fixes the following warning on boot: [ 0.307739] omap_hwmod: mcbsp2: _wait_target_ready failed: -16 [ 0.307769] omap_hwmod: mcbsp2: cannot be enabled for reset (3) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: fix ti_clk_get_reg_addr error handlingTero Kristo2015-03-248-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | There is a case where NULL can be a valid return value for ti_clk_get_reg_addr, specifically the case where both the provider index and register offsets are zero. In this case, the current error checking against a NULL pointer will fail. Thus, change the API to return a ERR_PTR value in an error case, and change all the users of this API to check against IS_ERR instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Michael Turquette <mturquette@linaro.org>
* | clk: ti: Fix FAPLL parent enable bit handlingTony Lindgren2015-02-251-3/+3
|/ | | | | | | | | | | | | | | Commit 163152cbbe32 ("clk: ti: Add support for FAPLL on dm816x") added basic support for the FAPLL on dm818x, but has a bug for the parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3) but the code is doing a shift on it. This means the parent PLL won't get disabled even if all it's child synthesizers are disabled. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: omap: compile legacy omap3 clocks conditionallyArnd Bergmann2015-02-036-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'ARM: OMAP3: legacy clock data move under clk driver' patch series causes build errors when CONFIG_OMAP3 is not set: drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll': drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function) const struct clk_ops *ops = &omap3_dpll_ck_ops; ^ drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function) ops = &omap3_dpll_per_ck_ops; ^ drivers/built-in.o: In function `ti_clk_register_gate': drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait' drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait' -in.o: In function `ti_clk_register_interface': drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait' drivers/clk/ti/interface.c:100: undefined reference to `clkhwops_am35xx_ipss_wait' drivers/built-in.o: In function `ti_clk_register_composite': :(.text+0x3da768): undefined reference to `ti_clk_build_component_gate' In order to fix that problem, this patch makes the omap3 legacy code compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* Merge branch 'clk-omap-legacy' into clk-nextMichael Turquette2015-02-0210-73/+5504
|\ | | | | | | | | Conflicts: arch/arm/mach-omap2/cclock3xxx_data.c
| * clk: ti: add omap3 legacy clock dataTero Kristo2015-01-302-1/+4655
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduces omap3 legacy clock data under clock driver. The clock data is also in new format, which makes it possible to get rid of the clk-private.h header. This patch also introduces SoC specific init functions that shall be called from the low level init. The data format used in this file has two possible evolution paths; it can either be removed completely once no longer needed, or it will be possible to retain the format and modify the TI clock driver to be a loadable module at some point. The actual path to be followed will be decided later. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: composite: add support for legacy composite clock initTero Kristo2015-01-303-4/+46
| | | | | | | | | | | | | | | | | | Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: dpll: add support for legacy DPLL initTero Kristo2015-01-303-11/+113
| | | | | | | | | | | | | | | | | | Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: divider: add support for legacy divider initTero Kristo2015-01-303-1/+136
| | | | | | | | | | | | | | | | | | Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: interface: add support for legacy interface clock initTero Kristo2015-01-303-24/+76
| | | | | | | | | | | | | | | | | | | | | | Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. The interface clock descriptor itself is overloading the gate clock descriptor, thus it needs to be called from the gate setup. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: gate: add support for legacy gate initTero Kristo2015-01-303-30/+133
| | | | | | | | | | | | | | | | | | Legacy clock data is initialialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: mux: add support for legacy mux initTero Kristo2015-01-303-2/+75
| | | | | | | | | | | | | | | | | | Legacy clock data is initialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: ti: add core support for initializing legacy clocksTero Kristo2015-01-302-0/+270
| | | | | | | | | | | | | | | | | | | | | | Legacy clock data for OMAP3 is being moved under clock driver, thus base support for this is needed. This patch adds basic definitions for clock init descriptors and core infrastructure for initialization, which will be called from the OMAP3 clock init. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: ti: Drop use of clk-private.hStephen Boyd2015-01-273-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | These modules don't need to include clk-private.h. Replace the include with clk.h because these modules are clock consumers and also include clk-provider.h in clk/ti.h because struct clk_hw_omap has a struct clk_hw embedded in it. Cc: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: ti: Initialize clocks for dm816xTony Lindgren2015-01-203-8/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocks on ti81xx are not compatible with omap3. On dm816x the clock source is a FAPLL (Flying Adder PLL), and on dm814x there seems to be an APLL (All Digital PLL). Let's fix up things for dm816x in preparation for adding the FAPLL support. As we already have a dummy ti81xx_dt_clk_init() in place, let's use that for now to avoid adding a dependency to the omap patches. Later on if somebody adds dm814x support we can split the ti81xx_dt_clk_init() clock init function as needed. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* | clk: ti: Add support for FAPLL on dm816xTony Lindgren2015-01-202-0/+411
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL) that does not seem to be used on the other omap variants. There are four instances of the FAPLL on dm816x that each have three to seven child synthesizers. I've set up the FAPLL as a single fapll.c driver. Later on we could potentially have the PLL code generic. To do that, we would have to consider the following: 1. Setting the PLL to bypass mode also sets the child synthesizers into bypass mode. As the bypass rate can also be generated by the PLL in regular mode, there's no way for the child synthesizers to detect the bypass mode based on the parent clock rate. 2. The PLL registers control the power for each of the child syntheriser. Note that the clocks are currently still missing the set_rate implementation so things are still running based on the bootloader values. That's OK for now as most of the outputs have dividers and those can be set using the existing TI component clock code. I have verified that the extclk rates are correct for a few clocks, so adding the set_rate support should be fairly trivial later on. This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02 patches published at: http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()Tero Kristo2014-11-131-0/+15
| | | | | | | | | | | Currently, DPLLs are hiding the gory details of switching parent within set_rate, which confuses the common clock code and is wrong. Fixed by applying the new determine_rate() and set_rate_and_parent() functionality to any clock-ops previously using the broken approach. This patch also removes the broken legacy code. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'for-v3.18/ti-clk-driver' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-09-304-27/+52
|\ | | | | | | clk-next
| * clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safePeter Ujfalusi2014-09-291-0/+1
| | | | | | | | | | | | | | It is safe to call the pm sync calls in interrupt context in this driver. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: LLVMLinux: Move __init outside of type definitionBehan Webster2014-09-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As written, the __init for ti_clk_get_div_table is in the middle of the return type. The gcc documentation indicates that section attributes should be added to the end of the function declaration: extern void foobar (void) __attribute__ ((section ("bar"))); However gcc seems to be very permissive with where attributes can be placed. clang on the other hand isn't so permissive, and fails if you put the section definition in the middle of the return type: drivers/clk/ti/divider.c:298:28: error: expected ';' after struct static struct clk_div_table ^ ; drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this declaration [-Wmissing-declarations] static struct clk_div_table ^ drivers/clk/ti/divider.c:299:9: error: type specifier missing, defaults to 'int' [-Werror,-Wimplicit-int] __init *ti_clk_get_div_table(struct device_node *node) ~~~~~~ ^ drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types] return table; ^~~~~ drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types] *table = ti_clk_get_div_table(node); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 warnings and 2 errors generated. By convention, most of the kernel code puts section attributes between the return type and function name. In the case where the return type is a pointer, it's important to place the '*' on left of the __init. This updated code works for both gcc and clang. Signed-off-by: Behan Webster <behanw@converseincode.com> Reviewed-by: Mark Charlebois <charlebm@gmail.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: consider the fact that of_clk_get() might return an errorSebastian Andrzej Siewior2014-09-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I "forgot" to update the dtb and the kernel crashed: |Unable to handle kernel NULL pointer dereference at virtual address 0000002e |PC is at __clk_get_flags+0x4/0xc |LR is at ti_dt_clockdomains_setup+0x70/0xe8 because I did not have the clock nodes. of_clk_get() returns an error pointer which is not checked here. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * clk: ti: dra7-atl-clock: fix a memory leakTero Kristo2014-09-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | of_clk_add_provider makes an internal copy of the parent_names property while its called, thus it is no longer needed after this call and can be freed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
| * clk: ti: change clock init to use generic of_clk_initTero Kristo2014-09-291-25/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the TI clock driver initialized all the clocks hierarchically under each separate clock provider node. Now, each clock that requires IO access will instead check their parent node to find out which IO range to use. This patch allows the TI clock driver to use a few new features provided by the generic of_clk_init, and also allows registration of clock nodes outside the clock hierarchy (for example, any external clocks.) Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Stefan Assmann <sassmann@kpanic.de> Acked-by: Tony Lindgren <tony@atomide.com>
* | clk: Remove .owner field for driverKiran Padwal2014-09-261-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: ti: dra7-atl: Provide error check for incoming parameters in set_rateNishanth Menon2014-08-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Check for valid parameters in check rate. Else, we end up getting errors. This occurs as part of the inital clock tree update of child clock nodes where new_rate could be 0 for non functional clocks. Fixes: 9ac33b0ce81fa48 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | clk: ti: divider: Provide error check for incoming parameters in set_rateNishanth Menon2014-08-211-1/+6
|/ | | | | | | | | | | | | | | | | | | | Check for valid parameters in check rate. Else, we end up getting errors like: [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1 [ 0.000000] [<c0015160>] (unwind_backtrace) from [<c0011978>] (show_stack+0x10/0x14) [ 0.000000] [<c0011978>] (show_stack) from [<c055f5f4>] (dump_stack+0x78/0x94) [ 0.000000] [<c055f5f4>] (dump_stack) from [<c02e17cc>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02e17cc>] (Ldiv0) from [<c047d228>] (ti_clk_divider_set_rate+0x14/0x14c) [ 0.000000] [<c047d228>] (ti_clk_divider_set_rate) from [<c047a938>] (clk_change_rate+0x138/0x180) [ 0.000000] [<c047a938>] (clk_change_rate) from [<c047a908>] (clk_change_rate+0x108/0x180) This occurs as part of the inital clock tree update of child clock nodes where new_rate could be 0 for non functional clocks. Fixes: b4761198bfaf296 ("CLK: ti: add support for ti divider-clock") Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* Merge tag 'clk-for-linus-3.17' of ↵Linus Torvalds2014-08-041-0/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.17 are mostly additions of new clock drivers and fixes/enhancements to existing clock drivers. There are also some non-critical fixes and improvements to the framework core. Changes to the clock framework core include: - improvements to printks on errors - flattening the previously hierarchal structure of per-clock entries in debugfs - allow per-clock debugfs entries that are specific to a particular clock driver - configure initial clock parent and/or initial clock rate from Device Tree - several feature enhancements to the composite clock type - misc fixes New clock drivers added include: - TI Palmas PMIC - Allwinner A23 SoC - Qualcomm APQ8084 and IPQ8064 SoCs - Rockchip rk3188, rk3066 and rk3288 SoCs - STMicroelectronics STiH407 SoC - Cirrus Logic CLPS711X SoC Many fixes, feature enhancements and further clock tree support for existing clock drivers also were merged, such as Samsung's "ARMCLK down" power saving feature for their Exynos4 & Exynos5 SoCs" * tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: Add missing of_clk_set_defaults export clk: checking wrong variable in __set_clk_parents() clk: Propagate any error return from debug_init() clk: clps711x: Add DT bindings documentation clk: Add CLPS711X clk driver clk: st: Use round to closest divider flag clk: st: Update frequency tables for fs660c32 and fs432c65 clk: st: STiH407: Support for clockgenA9 clk: st: STiH407: Support for clockgenD0/D2/D3 clk: st: STiH407: Support for clockgenC0 clk: st: Add quadfs reset handling clk: st: Add polarity bit indication clk: st: STiH407: Support for clockgenA0 clk: st: STiH407: Support for A9 MUX Clocks clk: st: STiH407: Support for Flexgen Clocks clk: st: Adds Flexgen clock binding clk: st: Remove uncessary (void *) cast clk: st: use static const for clkgen_pll_data tables clk: st: use static const for stm_fs tables clk: st: Update ST clock binding documentation ...
| * Merge branch 'for-v3.17/ti-clk-driver' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-07-261-0/+11
| |\ | | | | | | | | | clk-next-ti
| | * CLK: ti: dra7: Initialize USB_DPLLRoger Quadros2014-07-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB_DPLL must be initialized and locked at boot so that USB modules can work. Also program USB_DLL_M2 output to half rate. CC: Mike Turquette <mturquette@linaro.org> CC: Tero Kristo <t-kristo@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | | clk: ti: clk-7xx: Correct ABE DPLL configurationPeter Ujfalusi2014-07-311-1/+6
|/ / | | | | | | | | | | | | | | | | | | | | | | ABE DPLL frequency need to be lowered from 361267200 to 180633600 to facilitate the ATL requironments. The dpll_abe_m2x2_ck clock need to be set to double of ABE DPLL rate in order to have correct clocks for audio. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clockTomi Valkeinen2014-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When setting the rate of a clock, by default the clock framework will change the parent of the clock to the most suitable one in __clk_mux_determine_rate() (most suitable by looking at the clock rate). This is a rather dangerous default, and causes problems on AM43x when using display and ethernet. There are multiple ways to select the clock muxes on AM43x, and some of those clock paths have the same source clocks for display and ethernet. When changing the clock rate for the display subsystem, the clock framework decides to change the display mux from the dedicated display PLL to a shared PLL which is used by the ethernet, and then changes the rate of the shared PLL, breaking the ethernet. As I don't think there ever is a case where we want the clock framework to automatically change the parent clock of a clock mux, this patch sets the CLK_SET_RATE_NO_REPARENT for all ti,mux-clocks. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabledRoger Quadros2014-06-191-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define ti_clk_register_dpll_x2() and of_ti_am3_dpll_x2_setup() if AM43XX is defined. Fixes the below boot issue. [ 2.157258] gpmc_l3_clk not enabled [ 2.161194] gpmc_l3_clk not enabled [ 2.164896] Division by zero in kernel. [ 2.169055] CPU: 0 PID: 321 Comm: kworker/u2:2 Tainted: G W 3.16.0-rc1-00008-g4c0e520 #273 [ 2.178880] Workqueue: deferwq deferred_probe_work_func [ 2.184459] [<c001477c>] (unwind_backtrace) from [<c001187c>] (show_stack+0x10/0x14) [ 2.192752] [<c001187c>] (show_stack) from [<c0530f28>] (dump_stack+0x80/0x9c) [ 2.200486] [<c0530f28>] (dump_stack) from [<c02c867c>] (Ldiv0+0x8/0x10) [ 2.207678] [<c02c867c>] (Ldiv0) from [<c0022da0>] (gpmc_calc_divider+0x24/0x40) [ 2.215490] [<c0022da0>] (gpmc_calc_divider) from [<c0022e20>] (gpmc_cs_set_timings+0x18/0x474) [ 2.224783] [<c0022e20>] (gpmc_cs_set_timings) from [<c003069c>] (gpmc_nand_init+0x74/0x1a8) [ 2.233791] [<c003069c>] (gpmc_nand_init) from [<c0024668>] (gpmc_probe+0x52c/0x874) [ 2.242089] [<c0024668>] (gpmc_probe) from [<c0349218>] (platform_drv_probe+0x18/0x48) [ 2.250534] [<c0349218>] (platform_drv_probe) from [<c0347d88>] (driver_probe_device+0x104/0x22c) [ 2.259988] [<c0347d88>] (driver_probe_device) from [<c03464dc>] (bus_for_each_drv+0x44/0x8c) [ 2.269087] [<c03464dc>] (bus_for_each_drv) from [<c0347c4c>] (device_attach+0x74/0x8c) [ 2.277620] [<c0347c4c>] (device_attach) from [<c0347380>] (bus_probe_device+0x88/0xb0) [ 2.286074] [<c0347380>] (bus_probe_device) from [<c0347768>] (deferred_probe_work_func+0x60/0x90) [ 2.295611] [<c0347768>] (deferred_probe_work_func) from [<c004ef50>] (process_one_work+0x1b4/0x4bc) [ 2.305288] [<c004ef50>] (process_one_work) from [<c004f3d4>] (worker_thread+0x148/0x550) [ 2.313954] [<c004f3d4>] (worker_thread) from [<c0055a48>] (kthread+0xc8/0xe4) [ 2.321628] [<c0055a48>] (kthread) from [<c000e648>] (ret_from_fork+0x14/0x2c) Signed-off-by: Roger Quadros <rogerq@ti.com> Reported-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | clk: ti: dra7: return error code in failure caseJulia Lawall2014-06-191-4/+2Star
| | | | | | | | | | | | | | | | | | Add a returned error code in the MAX_APLL_WAIT_TRIES case. Remove the updating of the return variable r to 0 if MAX_APLL_WAIT_TRIES is not yet reached, because r is already 0 at this point. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Tero Kristo <t-kristo@ti.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-07 23:59:04 +0200