summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | | * | | | dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet2019-04-011-0/+20
| | | * | | | clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock idNeil Armstrong2019-03-191-1/+0Star
| | | |/ / /
| | * | | | clk: highbank: Convert to CLK_IS_CRITICALStephen Boyd2019-03-061-13/+10Star
| * | | | | clk: Document and simplify clk_core_get_rate_nolock()Stephen Boyd2019-02-021-15/+10Star
| * | | | | clk: nxp: Drop 'flags' on fixed_rate clk macroStephen Boyd2019-01-241-4/+3Star
| * | | | | clk: Document __clk_mux_determine_rate()Stephen Boyd2019-01-241-0/+6
| * | | | | clk: Document deprecated thingsStephen Boyd2019-01-241-5/+10
| | | | | |
| \ \ \ \ \
| \ \ \ \ \
| \ \ \ \ \
| \ \ \ \ \
| \ \ \ \ \
| \ \ \ \ \
| \ \ \ \ \
*-------. \ \ \ \ \ Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-...Stephen Boyd2019-05-0752-203/+4615
|\ \ \ \ \ \ \ \ \ \
| | | | | * | | | | | clk: imx: correct pfdv2 gate_bit/vld_bit operationsAnson Huang2019-05-031-5/+5
| | | | | * | | | | | clk: imx: clk-pllv3: mark expected switch fall-throughsGustavo A. R. Silva2019-05-031-0/+2
| | | | | * | | | | | clk: imx8mq: Add dsi_ipg_divGuido Günther2019-05-021-0/+1
| | | | | * | | | | | clk: imx: pllv4: add fractional-N pll supportAnson Huang2019-05-011-9/+63
| | | | | * | | | | | clk: imx: keep uart clock on during system bootJacky Bai2019-04-301-0/+16
| | | | | * | | | | | clk: imx: correct i.MX7D AV PLL num/denom offsetAnson Huang2019-04-303-10/+24
| | | | | * | | | | | clk: imx6sll: Fix mispelling uart4_serial as serailLeonard Crestez2019-04-251-1/+1
| | | | | * | | | | | clk: imx: pll14xx: drop unused variablePeng Fan2019-04-251-4/+2Star
| | | | | * | | | | | Merge tag 'clk-imx7ulp-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/...Stephen Boyd2019-04-251-1/+0Star
| | | | | |\ \ \ \ \ \
| | | | | | * | | | | | clk: imx7ulp: remove snvs clockAnson Huang2019-03-201-1/+0Star
| | | | | | | |_|/ / / | | | | | | |/| | | |
| | | | | * | | | | | Merge tag 'clk-imx5-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/sha...Stephen Boyd2019-04-252-15/+46
| | | | | |\ \ \ \ \ \
| | | | | | * | | | | | clk: imx: rename clk-imx51-imx53.c to clk-imx5.cShawn Guo2019-04-152-1/+1
| | | | | | * | | | | | clk: imx5: Fix i.MX50 ESDHC clock registersJonathan Neuschäfer2019-04-031-10/+30
| | | | | | * | | | | | clk: imx5: Fix i.MX50 mainbus clock registersJonathan Neuschäfer2019-04-031-4/+15
| | | | | | |/ / / / /
| | | | | * / / / / / clk: imx: Remove unused imx_get_clk_hw_fixedAbel Vesa2019-03-261-5/+0Star
| | | | | |/ / / / /
| | | | * / / / / / clock: milbeaut: Add Milbeaut M10V clock controllerSugaya Taichi2019-04-262-0/+664
| | | | |/ / / / /
| | | * | | | | | clk: mediatek: add clock driver for MT8516Fabien Parent2019-04-253-0/+824
| | | * | | | | | clk: mediatek: Allow changing PLL rate when it is offJames Liao2019-04-111-11/+2Star
| | | * | | | | | clk: mediatek: Add MT8183 clock supportWeiyi Lu2019-04-1115-0/+2196
| | | * | | | | | clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2019-04-112-6/+12
| | | * | | | | | clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2019-04-112-4/+13
| | | * | | | | | clk: mediatek: Add new clkmux register APIOwen Chen2019-04-113-1/+314
| | | * | | | | | clk: mediatek: Disable tuner_en before change PLL rateOwen Chen2019-04-111-14/+34
| | | |/ / / / /
| | * | | | | | clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998Marc Gonzalez2019-04-111-1/+1
| | * | | | | | clk: qcom: Add QCS404 TuringCCBjorn Andersson2019-04-113-0/+177
| | * | | | | | clk: qcom: branch: Add AON clock opsBjorn Andersson2019-04-112-0/+7
| | * | | | | | clk: qcom: gcc-qcs404: Add CDSP related clocks and resetsBjorn Andersson2019-04-111-0/+90
| | |/ / / / /
| * | | | | | clk: renesas: rcar-gen3: Remove unused variableStephen Boyd2019-04-111-1/+0Star
| * | | | | | clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return valueTakeshi Kihara2019-04-041-16/+14Star
| * | | | | | clk: renesas: r8a77980: Fix RPC-IF module clock's parentSergei Shtylyov2019-04-021-1/+1
| * | | | | | clk: renesas: rcar-gen3: Rename DRIF clocksTakeshi Kihara2019-04-024-34/+35
| * | | | | | clk: renesas: rcar-gen3: Correct parent clock of Audio-DMACTakeshi Kihara2019-04-027-11/+11
| * | | | | | clk: renesas: rcar-gen3: Correct parent clock of SYS-DMACTakeshi Kihara2019-04-024-8/+8
| * | | | | | clk: renesas: rcar-gen3: Correct parent clock of HS-USBKazuya Mizuguchi2019-04-026-7/+7
| * | | | | | clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCIKazuya Mizuguchi2019-04-026-12/+12
| * | | | | | clk: renesas: r8a774c0: Add Z2 clockSimon Horman2019-04-021-0/+1
| * | | | | | clk: renesas: r8a77990: Add Z2 clockTakeshi Kihara2019-04-021-0/+1
| * | | | | | clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parentsSimon Horman2019-04-021-2/+2
| * | | | | | clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2Simon Horman2019-04-025-5/+3Star
| * | | | | | clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offsetSimon Horman2019-04-026-20/+13Star
| * | | | | | clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisorTakeshi Kihara2019-04-026-16/+28
| * | | | | | clk: renesas: r9a06g032: Add missing PCI USB clockGareth Williams2019-04-021-0/+1
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-23 14:21:10 +0200