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| | | | | * | | | clk: qoriq: add more PLL divider clocks supportYuantian Tang2019-04-251-2/+3
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| | | | * | | | clk: rockchip: undo several noc and special clocks as critical on rk3288Douglas Anderson2019-04-231-9/+4Star
| | | | * | | | clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao2019-04-122-3/+29
| | | | * | | | clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson2019-04-121-0/+11
| | | | * | | | clk: rockchip: Limit use of USB PHY clock to USB on rk3288Matthias Kaehlcke2019-04-121-2/+2
| | | | * | | | clk: rockchip: Fix video codec clocks on rk3288Douglas Anderson2019-04-121-2/+2
| | | | * | | | clk: rockchip: Make rkpwm a critical clock on rk3288Douglas Anderson2019-04-111-1/+3
| | | | * | | | clk: rockchip: fix wrong clock definitions for rk3328Jonas Karlman2019-03-181-9/+9
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| | | * | | | clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard2019-04-101-4/+0Star
| | | * | | | clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclkChen-Yu Tsai2019-04-091-2/+3
| | | * | | | clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rateJernej Skrabec2019-04-041-3/+3
| | | * | | | clk: sunxi-ng: h6: Preset hdmi-cec clock parentJernej Skrabec2019-04-031-0/+11
| | | * | | | clk: sunxi: Add Kconfig optionsMaxime Ripard2019-03-213-22/+71
| | | * | | | clk: sunxi-ng: f1c100s: fix USB PHY gate bit offsetIcenowy Zheng2019-03-181-1/+1
| | | * | | | clk: sunxi-ng: Allow DE clock to set parent rateJernej Skrabec2019-03-183-3/+5
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| | * / / / clk: lochnagar: Add support for the Cirrus Logic LochnagarCharles Keepax2019-04-233-0/+344
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| * / / / clk: hi3660: Mark clk_gate_ufs_subsys as criticalLeo Yan2019-04-201-1/+5
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*-------. \ \ \ Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd2019-05-0712-90/+178
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| | | | | * | | | clk: zynqmp: use structs for clk query responsesMichael Tretter2019-04-192-77/+99
| | | | | * | | | clk: zynqmp: fix check for fractional clockMichael Tretter2019-04-111-3/+6
| | | | | * | | | clk: zynqmp: do not export zynqmp_clk_register_* functionsMichael Tretter2019-04-112-2/+0Star
| | | | | * | | | clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parentsMichael Tretter2019-04-111-1/+1
| | | | | * | | | drivers: clk: Update clock driver to handle clock attributeRajan Vaja2019-04-111-13/+29
| | | | | * | | | drivers: clk: zynqmp: Allow zero divisor valueRajan Vaja2019-04-111-0/+7
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| | | | * / / / clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil2019-04-111-0/+6
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| | | * / / / clk: samsung: exynos5410: Add gate clock for ADCKrzysztof Kozlowski2019-03-221-0/+1
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| | * / / / clk: Aspeed: Setup video engine clockingEddie James2019-04-181-3/+39
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| * | | | clk: mvebu: fix spelling mistake "gatable" -> "gateable"Colin Ian King2019-04-182-3/+3
| * | | | clk: ux500: add range to usleep_rangeNicholas Mc Guire2019-04-111-1/+2
| * | | | clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing2019-04-111-1/+1
| * | | | clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5Ding Xiang2019-04-111-3/+1Star
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*-----. \ \ \ Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be'...Stephen Boyd2019-05-0729-626/+2363
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| | | | * | | | clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski2019-04-2318-68/+68
| | | | * | | | clk: mux: add explicit big endian supportJonas Gorski2019-04-231-3/+19
| | | | * | | | clk: multiplier: add explicit big endian supportJonas Gorski2019-04-231-3/+19
| | | | * | | | clk: gate: add explicit big endian supportJonas Gorski2019-04-231-3/+19
| | | | * | | | clk: fractional-divider: add explicit big endian supportJonas Gorski2019-04-231-3/+19
| | | | * | | | clk: divider: add explicit big endian supportJonas Gorski2019-04-231-4/+20
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| | | * | | | clk: meson: axg-audio: add g12a supportMaxime Jourdan2019-04-082-8/+239
| | | * | | | clk: meson: axg-audio: don't register inputs in the onecell dataJerome Brunet2019-04-082-44/+6Star
| | | * | | | clk: meson: axg_audio: replace prefix axg by audJerome Brunet2019-04-081-482/+482
| | | * | | | clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl2019-04-012-1/+328
| | | * | | | clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl2019-04-012-1/+175
| | | * | | | clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl2019-04-012-1/+66
| | | * | | | clk: meson: meson8b: use a separate clock table for Meson8m2Martin Blumenstingl2019-04-011-1/+192
| | | * | | | clk: meson-g12a: add video decoder clocksMaxime Jourdan2019-04-012-1/+170
| | | * | | | clk: meson-g12a: add PCIE PLL clocksNeil Armstrong2019-04-012-1/+122
| | | * | | | clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLLNeil Armstrong2019-04-012-0/+27
| | | * | | | clk: meson: g12a: add cpu clocksNeil Armstrong2019-04-012-1/+371
| | | * | | | dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong2019-04-011-1/+0Star
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