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| | | * | | | clk: at91: master: Add sam9x60 supportAlexandre Belloni2019-04-252-3/+6
| | | * | | | clk: at91: usb: Add sam9x60 supportAlexandre Belloni2019-04-252-6/+30
| | | * | | | clk: at91: allow configuring generated PCR layoutAlexandre Belloni2019-04-254-24/+29
| | | * | | | clk: at91: allow configuring peripheral PCR layoutAlexandre Belloni2019-04-256-22/+71
| | | * | | | clk: at91: sckc: handle different RC startup timeAlexandre Belloni2019-04-251-2/+15
| | | * | | | clk: at91: modernize sckc bindingAlexandre Belloni2019-04-251-89/+36Star
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| | * | | | clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko2019-04-251-1/+2
| | * | | | clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko2019-04-251-1/+4
| | * | | | clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko2019-04-251-7/+10
| | * | | | clk: tegra: emc: Support multiple RAM codesDmitry Osipenko2019-04-251-14/+23
| | * | | | clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko2019-04-251-2/+0Star
| | * | | | clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko2019-04-251-2/+1Star
| | * | | | clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko2019-04-251-2/+2
| | * | | | clk: tegra: Don't enable already enabled PLLsDmitry Osipenko2019-04-201-13/+37
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| * | | | clk: stm32mp1: Add ddrperfm clockGabriel Fernandez2019-04-291-0/+3
| * | | | clk: stm32: Introduce clocks of STM32F769 boardGabriel Fernandez2019-04-251-8/+299
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*-------. \ \ \ Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' a...Stephen Boyd2019-05-0717-66/+576
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| | | | | * | | | clk: qoriq: increase array size of cmux_to_groupYogesh Gaur2019-04-251-2/+2
| | | | | * | | | clk: qoriq: Add ls1028a clock configurationYuantian Tang2019-04-251-0/+68
| | | | | * | | | clk: qoriq: add more PLL divider clocks supportYuantian Tang2019-04-251-2/+3
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| | | | * | | | clk: rockchip: undo several noc and special clocks as critical on rk3288Douglas Anderson2019-04-231-9/+4Star
| | | | * | | | clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao2019-04-122-3/+29
| | | | * | | | clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288Douglas Anderson2019-04-121-0/+11
| | | | * | | | clk: rockchip: Limit use of USB PHY clock to USB on rk3288Matthias Kaehlcke2019-04-121-2/+2
| | | | * | | | clk: rockchip: Fix video codec clocks on rk3288Douglas Anderson2019-04-121-2/+2
| | | | * | | | clk: rockchip: Make rkpwm a critical clock on rk3288Douglas Anderson2019-04-111-1/+3
| | | | * | | | clk: rockchip: fix wrong clock definitions for rk3328Jonas Karlman2019-03-181-9/+9
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| | | * | | | clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard2019-04-101-4/+0Star
| | | * | | | clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclkChen-Yu Tsai2019-04-091-2/+3
| | | * | | | clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rateJernej Skrabec2019-04-041-3/+3
| | | * | | | clk: sunxi-ng: h6: Preset hdmi-cec clock parentJernej Skrabec2019-04-031-0/+11
| | | * | | | clk: sunxi: Add Kconfig optionsMaxime Ripard2019-03-213-22/+71
| | | * | | | clk: sunxi-ng: f1c100s: fix USB PHY gate bit offsetIcenowy Zheng2019-03-181-1/+1
| | | * | | | clk: sunxi-ng: Allow DE clock to set parent rateJernej Skrabec2019-03-183-3/+5
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| | * / / / clk: lochnagar: Add support for the Cirrus Logic LochnagarCharles Keepax2019-04-233-0/+344
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| * / / / clk: hi3660: Mark clk_gate_ufs_subsys as criticalLeo Yan2019-04-201-1/+5
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*-------. \ \ \ Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd2019-05-0712-90/+178
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| | | | | * | | | clk: zynqmp: use structs for clk query responsesMichael Tretter2019-04-192-77/+99
| | | | | * | | | clk: zynqmp: fix check for fractional clockMichael Tretter2019-04-111-3/+6
| | | | | * | | | clk: zynqmp: do not export zynqmp_clk_register_* functionsMichael Tretter2019-04-112-2/+0Star
| | | | | * | | | clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parentsMichael Tretter2019-04-111-1/+1
| | | | | * | | | drivers: clk: Update clock driver to handle clock attributeRajan Vaja2019-04-111-13/+29
| | | | | * | | | drivers: clk: zynqmp: Allow zero divisor valueRajan Vaja2019-04-111-0/+7
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| | | | * / / / clk: ingenic: jz4725b: Add UDC PHY clockPaul Cercueil2019-04-111-0/+6
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| | | * / / / clk: samsung: exynos5410: Add gate clock for ADCKrzysztof Kozlowski2019-03-221-0/+1
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| | * / / / clk: Aspeed: Setup video engine clockingEddie James2019-04-181-3/+39
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| * | | | clk: mvebu: fix spelling mistake "gatable" -> "gateable"Colin Ian King2019-04-182-3/+3
| * | | | clk: ux500: add range to usleep_rangeNicholas Mc Guire2019-04-111-1/+2
| * | | | clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing2019-04-111-1/+1
| * | | | clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5Ding Xiang2019-04-111-3/+1Star
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