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| * | | Merge branch 'clk-divider-container' into clk-nextStephen Boyd2018-01-276-9/+9
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| | * | | clk: divider: fix incorrect usage of container_ofJerome Brunet2017-12-295-8/+7Star
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| *---. \ \ Merge branches 'clk-iproc', 'clk-mvebu' and 'clk-qcom-a53' into clk-nextStephen Boyd2018-01-2710-102/+737
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| | | | * | | clk: qcom: Add APCS clock controller supportGeorgi Djakov2018-01-023-0/+150
| | | | * | | clk: qcom: Add regmap mux-div clocks supportGeorgi Djakov2018-01-023-0/+276
| | | | * | | clk: qcom: Add A53 PLL supportGeorgi Djakov2018-01-023-0/+118
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| | | * / / clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()Gomonovych, Vasyl2017-12-281-4/+1Star
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| | * | | clk: iproc: Minor tidy up of iproc pll data structuresLori Hikichi2017-12-281-47/+36Star
| | * | | clk: iproc: Allow plls to do minor rate changes without resetLori Hikichi2017-12-281-0/+47
| | * | | clk: iproc: Fix error in the pll post divider rate calculationLori Hikichi2017-12-281-16/+17
| | * | | clk: iproc: Allow iproc pll to runtime calculate vco parametersLori Hikichi2017-12-283-35/+92
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| *-------. \ \ Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and 'clk...Stephen Boyd2018-01-277-41/+146
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| | | | | | * | | clk: pxa: unbreak lookup of CLK_POUTIgor Grinberg2017-12-281-1/+5
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| | | | | * | | clk: si5351: _si5351_clkout_reset_pll() can be staticWu Fengguang2017-12-281-1/+1
| | | | | * | | clk: si5351: Do not enable parent clocks on probeSergej Sawazki2017-12-221-26/+9Star
| | | | | * | | clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki2017-12-221-1/+1
| | | | | * | | clk: si5351: Apply PLL soft reset before enabling the outputsSergej Sawazki2017-12-221-0/+29
| | | | | * | | clk: si5351: Add DT property to enable PLL resetSergej Sawazki2017-12-221-0/+3
| | | | | * | | clk: si5351: implement remove handlerAlexey Khoroshilov2017-12-221-0/+13
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| | | | * | | clk: axi-clkgen: Round closest in round_rate() and recalc_rate()Lars-Peter Clausen2017-12-221-3/+7
| | | | * | | clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen2017-12-221-5/+24
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| | | * / / clk: Don't touch hardware when reparenting during registrationStephen Boyd2017-12-221-2/+5
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| | * | | clk: at91: pmc: Support backup for programmable clocksRomain Izard2017-12-223-0/+39
| | * | | clk: at91: pmc: Save SCSR during suspendRomain Izard2017-12-221-2/+2
| | * | | clk: at91: pmc: Wait for clocks when resumingRomain Izard2017-12-221-8/+16
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| *-------. \ \ Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and...Stephen Boyd2018-01-2729-81/+7213
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| | | | | | * | | clk: qcom: ipq8074: add misc resets for PCIE and NSSAbhishek Sahu2017-12-221-0/+42
| | | | | | * | | clk: qcom: ipq8074: add GP and Crypto clocksAbhishek Sahu2017-12-221-0/+199
| | | | | | * | | clk: qcom: ipq8074: add NSS ethernet port clocksAbhishek Sahu2017-12-221-0/+1288
| | | | | | * | | clk: qcom: ipq8074: add NSS clocksAbhishek Sahu2017-12-221-0/+1034
| | | | | | * | | clk: qcom: ipq8074: add PCIE, USB and SDCC clocksAbhishek Sahu2017-12-221-0/+994
| | | | | | * | | clk: qcom: ipq8074: add remaining PLL’sAbhishek Sahu2017-12-221-1/+191
| | | | | | * | | clk: qcom: ipq8074: fix missing GPLL0 divider widthAbhishek Sahu2017-12-221-0/+1
| | | | | | * | | clk: qcom: add parent map for regmap muxAbhishek Sahu2017-12-224-11/+18
| | | | | | * | | clk: qcom: add read-only divider operationsAbhishek Sahu2017-12-222-0/+30
| | | | | * | | | clk: imx51: uart4, uart5 gates only exist on imx50, imx53Philipp Zabel2017-12-221-4/+8
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| | | | * / | | clk: qoriq: add more divider clocks supportYuantian Tang2017-12-221-1/+8
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| | | * | | | clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocksGregory CLEMENT2017-12-221-4/+217
| | | * | | | clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFSGregory CLEMENT2017-12-221-9/+73
| | | * | | | clk: mvebu: armada-37xx-periph: cosmetic changesGregory CLEMENT2017-12-221-8/+9
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| | * | | | clk: sprd: add clocks support for SC9860Chunyan Zhang2017-12-223-0/+1987
| | * | | | clk: sprd: add adjustable pll supportChunyan Zhang2017-12-223-0/+375
| | * | | | clk: sprd: add composite clock supportChunyan Zhang2017-12-223-0/+112
| | * | | | clk: sprd: add divider clock supportChunyan Zhang2017-12-223-0/+166
| | * | | | clk: sprd: add mux clock supportChunyan Zhang2017-12-223-0/+151
| | * | | | clk: sprd: add gate clock supportChunyan Zhang2017-12-223-0/+171
| | * | | | clk: sprd: Add common infrastructureChunyan Zhang2017-12-226-0/+143
| | * | | | clk: move clock common macros out from vendor directoriesChunyan Zhang2017-12-222-47/+0Star
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| *-----. \ \ \ Merge branches 'clk-qcom-alpha-pll', 'clk-check-ops-ptr', 'clk-protect-rate' ...Stephen Boyd2018-01-2715-5241/+918Star
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| | | | | * | clk: ti: Drop legacy clk-3xxx-legacy codeTony Lindgren2017-12-148-5078/+0Star
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