| Commit message (Collapse) | Author | Age | Files | Lines |
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* clk-divider-container:
clk: divider: fix incorrect usage of container_of
Plus fixup sprd/div.c to pass the width too.
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divider_recalc_rate() is an helper function used by clock divider of
different types, so the structure containing the 'hw' pointer is not
always a 'struct clk_divider'
At the following line:
> div = _get_div(table, val, flags, divider->width);
in several cases, the value of 'divider->width' is garbage as the actual
structure behind this memory is not a 'struct clk_divider'
Fortunately, this width value is used by _get_val() only when
CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so
far when the structure is not a 'struct clk_divider'. This is probably
why we did not notice this bug before
Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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* clk-iproc:
clk: iproc: Minor tidy up of iproc pll data structures
clk: iproc: Allow plls to do minor rate changes without reset
clk: iproc: Fix error in the pll post divider rate calculation
clk: iproc: Allow iproc pll to runtime calculate vco parameters
* clk-mvebu:
clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()
* clk-qcom-a53:
clk: qcom: Add APCS clock controller support
clk: qcom: Add regmap mux-div clocks support
clk: qcom: Add A53 PLL support
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Add a driver for the APCS clock controller. It is part of the APCS
hardware block, which among other things implements also a combined
mux and half integer divider functionality. It can choose between a
fixed-rate clock or the dedicated APCS (A53) PLL. The source and the
divider can be set both at the same time.
This is required for enabling CPU frequency scaling on MSM8916-based
platforms.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Include rcg header for parent_map, drop
multiple unneeded includes, add COMPILE_TEST to APCS depends,
made tristate/modular]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add support for hardware that can switch both parent clock and divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and
old divider combinations.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Change a comment style, drop parent_map in
favor of a u32 array instead, export symbols for clk_ops and mux
function]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,
a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources
are connected to a mux and half-integer divider, which is feeding the
CPU cores.
This patch adds support for the primary CPU PLL which generates the
higher range of frequencies above 1GHz.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
[sboyd@codeaurora.org: Move to devm provider registration,
NUL terminate frequency table, made tristate/modular]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Fix ptr_ret.cocci warnings:
drivers/clk/mvebu/armada-37xx-periph.c:362:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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There were a few fields in the iproc pll data structures that were
holding information that was not true state information.
Using stack variables is sufficient and simplifies the structure.
There are not any functional changes in this commit.
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The iproc plls are capable of doing small rate changes without the
need for a full reset and re-lock procedure. This feature will
allow for small tweaks to the PLL rate to occur smoothly.
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The pll post divider code was using DIV_ROUND_UP when determining the
divider value best suited to produce the target frequency.
Using DIV_ROUND_CLOSEST will give us better divider values when
the division results in a small remainder.
Also, change the post divider clock over to the determine_rate api
instead of round_rate.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add the ability for the iproc pll to calculate the pll parameters at
runtime instead of only using predefined tables. This ability allows
the clock users to select from the full range of vco frequencies.
The old method of table based programming is retained so that existing
users will retain expected behavior. The flag IPROC_CLK_PLL_CALC_PARAM
will need to be set to enable the new runtime calculation method.
Currently, this is only being enabled for the audio pll.
This feature also revealed a problem with the driver using the
round_rate api. The round_rate api does not allow for frequencies larger
than 2^31 to be returned. Those large frequencies are interpreted as an
error code. Therefore, we are moving to the determine_rate api which
solves this problem.
Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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'clk-pxa' into clk-next
* clk-at91:
clk: at91: pmc: Support backup for programmable clocks
clk: at91: pmc: Save SCSR during suspend
clk: at91: pmc: Wait for clocks when resuming
* clk-imx7ulp:
clk: Don't touch hardware when reparenting during registration
* clk-axigen:
clk: axi-clkgen: Round closest in round_rate() and recalc_rate()
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()
* clk-si5351:
clk: si5351: _si5351_clkout_reset_pll() can be static
clk: si5351: Do not enable parent clocks on probe
clk: si5351: Rename internal plls to avoid name collisions
clk: si5351: Apply PLL soft reset before enabling the outputs
clk: si5351: Add DT property to enable PLL reset
clk: si5351: implement remove handler
* clk-pxa:
clk: pxa: unbreak lookup of CLK_POUT
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Since switching to clk drivers, the CLK_POUT cannot be searched for by
clk_get() API and thus it returns with ENOENT.
Register it with the clk_lookup and thus unbreak the users of it.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Fixes: b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs")
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The si5351 driver should not prepare or enable other clocks in the tree on
probe. Let the clients decide when to prepare or enable the clocks.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
[sboyd@codeaurora.org: Remove most of the .remove function too]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This drivers probe fails due to a clock name collision if a clock named
'plla' or 'pllb' is already registered when registering this drivers
internal plls.
Fix it by renaming internal plls to avoid name collisions.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The "Si5351A/B/C Data Sheet" states to apply a PLL soft reset before
enabling the output clocks [1]. This is required to get a deterministic
phase relationship between the output clocks.
Without resetting the PLL, the phase relationship between the clocks is
unpredictable. Fix this by resetting the PLL in si5351_clkout_prepare().
References:
[1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf
Figure 12 ("I2C Programming Procedure")
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Add optional output clock DT property to enable PLL reset when a clock
output is enabled.
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sergej Sawazki <sergej@taudac.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The driver has no remove function, so it does not cleanup
resources that are not under devm management.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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To minimize the rounding error round to the closest integer when
calculating the result in the recalc_rate() and set_rate() callbacks.
Also in order to improve precision multiply first and then divide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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If the nocount bit is set the divider is bypassed and the settings for the
divider count should be ignored and a divider value of 1 should be assumed.
Handle this correctly in the driver recalc_rate() callback.
While the driver sets up the part so that the read back dividers values
yield the correct result the power-on reset settings of the part might not
reflect this and hence calling e.g. clk_get_rate() without prior calls to
clk_set_rate() will yield the wrong result.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The orphan clocks reparent operation shouldn't touch the hardware
if clocks are enabled, otherwise it may get a chance to disable a
newly registered critical clock which triggers the warning below.
Assuming we have two clocks: A and B, B is the parent of A.
Clock A has flag: CLK_OPS_PARENT_ENABLE
Clock B has flag: CLK_IS_CRITICAL
Step 1:
Clock A is registered, then it becomes orphan.
Step 2:
Clock B is registered. Before clock B reach the critical clock enable
operation, orphan A will find the newly registered parent B and do
reparent operation, then parent B will be finally disabled in
__clk_set_parent_after() due to CLK_OPS_PARENT_ENABLE flag as there's
still no users of B which will then trigger the following warning.
WARNING: CPU: 0 PID: 0 at drivers/clk/clk.c:597 clk_core_disable+0xb4/0xe0
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.11.0-rc1-00056-gdff1f66-dirty #1373
Hardware name: Generic DT based system
Backtrace:
[<c010c4bc>] (dump_backtrace) from [<c010c764>] (show_stack+0x18/0x1c)
r6:600000d3 r5:00000000 r4:c0e26358 r3:00000000
[<c010c74c>] (show_stack) from [<c040599c>] (dump_stack+0xb4/0xe8)
[<c04058e8>] (dump_stack) from [<c0125c94>] (__warn+0xd8/0x104)
r10:c0c21cd0 r9:c048aa78 r8:00000255 r7:00000009 r6:c0c1cd90 r5:00000000
r4:00000000 r3:c0e01d34
[<c0125bbc>] (__warn) from [<c0125d74>] (warn_slowpath_null+0x28/0x30)
r9:00000000 r8:ef00bf80 r7:c165ac4c r6:ef00bf80 r5:ef00bf80 r4:ef00bf80
[<c0125d4c>] (warn_slowpath_null) from [<c048aa78>] (clk_core_disable+0xb4/0xe0)
[<c048a9c4>] (clk_core_disable) from [<c048be88>] (clk_core_disable_lock+0x20/0x2c)
r4:000000d3 r3:c0e0af00
[<c048be68>] (clk_core_disable_lock) from [<c048c224>] (clk_core_disable_unprepare+0x14/0x28)
r5:00000000 r4:ef00bf80
[<c048c210>] (clk_core_disable_unprepare) from [<c048c270>] (__clk_set_parent_after+0x38/0x54)
r4:ef00bd80 r3:000010a0
[<c048c238>] (__clk_set_parent_after) from [<c048daa8>] (clk_register+0x4d0/0x648)
r6:ef00d500 r5:ef00bf80 r4:ef00bd80 r3:ef00bfd4
[<c048d5d8>] (clk_register) from [<c048dc30>] (clk_hw_register+0x10/0x1c)
r9:00000000 r8:00000003 r7:00000000 r6:00000824 r5:00000001 r4:ef00d500
[<c048dc20>] (clk_hw_register) from [<c048e698>] (_register_divider+0xcc/0x120)
[<c048e5cc>] (_register_divider) from [<c048e730>] (clk_register_divider+0x44/0x54)
r10:00000004 r9:00000003 r8:00000001 r7:00000000 r6:00000003 r5:00000001
r4:f0810030
[<c048e6ec>] (clk_register_divider) from [<c0d3ff58>] (imx7ulp_clocks_init+0x558/0xe98)
r7:c0e296f8 r6:c165c808 r5:00000000 r4:c165c808
[<c0d3fa00>] (imx7ulp_clocks_init) from [<c0d24db0>] (of_clk_init+0x118/0x1e0)
r10:00000001 r9:c0e01f68 r8:00000000 r7:c0e01f60 r6:ef7f8974 r5:ef0035c0
r4:00000006
[<c0d24c98>] (of_clk_init) from [<c0d04a50>] (time_init+0x2c/0x38)
r10:efffed40 r9:c0d61a48 r8:c0e78000 r7:c0e07900 r6:ffffffff r5:c0e78000
r4:00000000
[<c0d04a24>] (time_init) from [<c0d00b8c>] (start_kernel+0x218/0x394)
[<c0d00974>] (start_kernel) from [<6000807c>] (0x6000807c)
r10:00000000 r9:410fc075 r8:6000406a r7:c0e0c930 r6:c0d61a44 r5:c0e07918
r4:c0e78294
We know that the clk isn't enabled with any sort of prepare_count
here so we don't need to enable anything to prevent a race. And
we're holding the prepare mutex so set_rate/set_parent can't race
here either. Based on an earlier patch by Dong Aisheng.
Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Reported-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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When an AT91 programmable clock is declared in the device tree, register
it into the Power Management Controller driver. On entering suspend mode,
the driver saves and restores the Programmable Clock registers to support
the backup mode for these clocks.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The contents of the System Clock Status Register (SCSR) needs to be
restored into the System Clock Enable Register (SCER).
As the bootloader will restore some clocks by itself, the issue can be
missed as only the USB controller, the LCD controller, the Image Sensor
controller and the programmable clocks will be impacted.
Fix the obvious typo in the suspend/resume code, as the IMR register
does not need to be saved twice.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Wait for the syncronization of all clocks when resuming, not only the
UPLL clock. Do not use regmap_read_poll_timeout, as it will call BUG()
when interrupts are masked, which is the case in here.
Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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and 'clk-qcom-ipq8074' into clk-next
* clk-spreadtrum:
clk: sprd: add clocks support for SC9860
clk: sprd: Add dt-bindings include file for SC9860
dt-bindings: Add Spreadtrum clock binding documentation
clk: sprd: add adjustable pll support
clk: sprd: add composite clock support
clk: sprd: add divider clock support
clk: sprd: add mux clock support
clk: sprd: add gate clock support
clk: sprd: Add common infrastructure
clk: move clock common macros out from vendor directories
* clk-mvebu-dvfs:
clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks
clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS
clk: mvebu: armada-37xx-periph: cosmetic changes
* clk-qoriq:
clk: qoriq: add more divider clocks support
* clk-imx:
clk: imx51: uart4, uart5 gates only exist on imx50, imx53
* clk-qcom-ipq8074:
clk: qcom: ipq8074: add misc resets for PCIE and NSS
dt-bindings: clock: qcom: add misc resets for PCIE and NSS
clk: qcom: ipq8074: add GP and Crypto clocks
clk: qcom: ipq8074: add NSS ethernet port clocks
clk: qcom: ipq8074: add NSS clocks
clk: qcom: ipq8074: add PCIE, USB and SDCC clocks
clk: qcom: ipq8074: add remaining PLL’s
dt-bindings: clock: qcom: add remaining clocks for IPQ8074
clk: qcom: ipq8074: fix missing GPLL0 divider width
clk: qcom: add parent map for regmap mux
clk: qcom: add read-only divider operations
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PCIE and NSS has MISC reset register in which single register has
multiple reset bit. The patch adds these resets with its
corresponding reset bits.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- It has 3 general purpose clock controller which supplies
the clock in GPIO pins.
- It has Crypto Engine which has AXI, AHB and Core clocks.
Other non APSS processors can also use Crypto Engine so
these clocks are marked as VOTED clocks.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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IPQ8074 has 6 ethernet ports which supports all ethernet speeds
from 10Mpbs to 10 Gpbs and each speed requires different clock
rates. Each port has separate TX and RX clocks. These clocks
use separate external UNIPHY PLL’s which will be registered with
separate NSS driver. The clock frequency is 125 Mhz for UNIPHY0
and 312.5 Mhz for UNIPHY1 and UNIPHY2.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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IPQ8074 has NSS (Network Switching System) which has 2 UBI cores
and hardware crypto engine. Some clocks are separate for each UBI
core and remaining NSS clocks are common. The BIAS_PLL (300 Mhz)
and BIAS_PLL_NSS_NOC (416.5 Mhz) are external fixed clocks and
will be registered from dtsi or NSS driver.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- It has 2 instances of PCIE which uses AXI, AHB, AUX, SYS NOC
AXI and PIPE clocks.
- It has 2 instances of USB 3.0 which uses AUX, SLEEP, PIPE,
SYS NOC, mock UTMI and master clocks.
- It has 2 instances of SDCC which uses APSS and AHB clock.
SDCC1 requires ICE core clock also.
- All the PIPE clocks are external clocks which will be
registered in clock framework by PHY drivers. The enabling
and disabling of PIPE RCG clocks are dependent upon PHY
initialization sequence so BRANCH_HALT_DELAY flag is required for
these clocks.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- GPLL2, GPLL4 and GPLL6 are general PLL clocks and parent
for all core peripherals.
- UBI PLL is mainly used by NSS (Network Switching System).
IPQ8074 has 2 instances of NSS UBI cores and UBI PLL will
be used to control the core frequency.
- NSS Crypto PLL is mainly used by NSS Crypto Engine which
supports the multiple cryptographic algorithm used in
Ethernet.
- IPQ8074 frequency plan does not require change in PLL post
dividers so marked the same as read-only.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Currently the driver assumes the register configuration value
is identical to its index in the parent map. This patch adds
the parent map field in regmap mux clock node which contains
the mapping of parent index with actual register configuration
value. If regmap node contains this parent map then the
configuration value will be taken from this
parent map instead of simply writing the index value.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Some of the divider settings are preconfigured and should not
be changed by the clock framework during frequency change. This
patch adds the read-only divider operation for QCOM dividers
which is equivalent to generic divider operations in
'commit 79c6ab509558 ("clk: divider: add CLK_DIVIDER_READ_ONLY flag")'.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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i.MX51 only has 3 UARTs and no CCGR7 register. In place of the CCGR7
register on i.MX50/i.MX53 that contains the ipg and per clock gates
for UARTs 4 and 5, on i.MX51 there is the CMEOR register.
Without this patch, the code disabling the UART clocks would also clear
the mod_en_ov_vpu bit in the CMEOR register, among others, which causes
register accesses to the VPU to lock up the system.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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When DVFS is enabled the CPU clock setting is done using an other set of
registers.
These Power Management registers are exposed through a syscon as they
will also be used by other drivers such as the cpufreq.
This patch add the possibility to modify the CPU frequency using the
associate load level matching the target frequency. Then all the
frequency switch is handle by the hardware.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
[sboyd@codeaurora.org: Grow a local variable for regmap pointer
to keep lines shorter]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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When DVFS will be enabled then the cpu clk will use a different set of
register at run time. That means that we won't be able to use the common
callback and need to use our own ones.
This patch prepares this change by switching on our own set of callbacks
without modifying the behavior of the clocks.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patches fixes few cosmetic issues such as alignment, blank lines
and required space.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patch added the list of clocks for Spreadtrum's SC9860 SoC,
together with clock initialization code.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Introduced a common adjustable pll clock driver for Spreadtrum SoCs.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patch introduced composite driver for Spreadtrum's SoCs. The
functions of this composite clock simply consist of divider and
mux clocks.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This is a feature that can also be found in sprd composite clocks,
provide a bunch of helpers that can be reused later on.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patch adds clock multiplexor support for Spreadtrum platforms,
the mux clocks also can be found in sprd composite clocks, so
provides two helpers that can be reused later on.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Some clocks on the Spreadtrum's SoCs are just simple gates. Add
support for those clocks.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Added Spreadtrum's clock driver framework together with common
structures and interface functions.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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These macros are used by more than one SoC vendor platforms, avoid to
have many copies of these code, this patch moves them to the common
header file which every clock drivers can access to.
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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and 'clk-omap' into clk-next
* clk-qcom-alpha-pll:
clk: qcom: add read-only alpha pll post divider operations
clk: qcom: support for 2 bit PLL post divider
clk: qcom: support Brammo type Alpha PLL
clk: qcom: support Huayra type Alpha PLL
clk: qcom: support for dynamic updating the PLL
clk: qcom: support for alpha mode configuration
clk: qcom: flag for 64 bit CONFIG_CTL
clk: qcom: fix 16 bit alpha support calculation
clk: qcom: support for alpha pll properties
* clk-check-ops-ptr:
clk: check ops pointer on clock register
* clk-protect-rate:
clk: fix set_rate_range when current rate is out of range
clk: add clk_rate_exclusive api
clk: cosmetic changes to clk_summary debugfs entry
clk: add clock protection mechanism to clk core
clk: use round rate to bail out early in set_rate
clk: rework calls to round and determine rate callbacks
clk: add clk_core_set_phase_nolock function
clk: take the prepare lock out of clk_core_set_parent
clk: fix incorrect usage of ENOSYS
* clk-omap:
clk: ti: Drop legacy clk-3xxx-legacy code
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We have now had omap3 booting in device tree only mode for a while
and all this code is unused.
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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