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* clk: sunxi: add PRCM (Power/Reset/Clock Management) clks supportBoris BREZILLON2014-06-114-0/+411
| | | | | | | | | | | | | | | | The PRCM (Power/Reset/Clock Management) unit provides several clock devices: - AR100 clk: used to clock the Power Management co-processor - AHB0 clk: used to clock the AHB0 bus - APB0 clk and gates: used to clk peripherals connected to the APB0 bus Add support for these clks in a separate driver so that they can be probed as platform devices instead of registered during early init. This is needed to be able to probe PRCM MFD subdevices. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sun6i: Protect SDRAM gating bitMaxime Ripard2014-06-111-0/+1
| | | | | | | | | Prevent the SDRAM controller from being gated by force-enabling it in the machine code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sun6i: Protect CPU clockMaxime Ripard2014-06-111-0/+1
| | | | | | | | | | | | Right now, AHB is an indirect child clock of the CPU clock. If that happens to change, since the CPU clock has no other consumers declared in Linux, it would be shut down, which is not really a good idea. Prevent this by forcing it enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Rework clock protection codeMaxime Ripard2014-06-111-28/+44
| | | | | | | | | | | | Since we start to have a lot of clocks to protect, some of them in a few SoCs only, it becomes difficult to handle the clock protection without having to add per machine exceptions. Add per-SoC data to tell which clock to leave enabled. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard2014-06-113-99/+121
| | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The gmac clock is pretty easy to deal with, since it's pretty much isolated and doesn't have any dependency on the other clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard2014-06-113-57/+74
| | | | | | | | | | | | Since we have a folder of our own, we can actually make use of it by splitting the huge clock file into several sub drivers. The main oscillator is pretty easy to deal with, since it's pretty much isolated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Remove calls to clk_putMaxime Ripard2014-06-111-6/+2Star
| | | | | | | | | | | Callers of clk_put must disable the clock first. This also means that as long as the clock is enabled the driver should hold a reference to that clock. Hence, the call to clk_put here are bogus and should be removed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* clk: sunxi: Implement A31 USB clockMaxime Ripard2014-06-111-0/+6
| | | | | | | | | | | The A31 USB clock slightly differ from its older counterparts, mostly because it has a different gate for each PHY, while the older one had a single gate for all the phy. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Emilio López <emilio@elopez.com.ar>
* Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-06-119-38/+874
|\ | | | | | | clk-next
| * CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher ↵Nishanth Menon2014-06-061-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | frequencies MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). So provide support to setup required data to handle Duty cycle by the setting up the minimum frequency for DPLL. 1.4GHz is common for all these devices and is based on Technical Reference Manual information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and equivalent information from DRA75x, DRA72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by: Nishanth Menon <nm@ti.com> [t-kristo@ti.com: updated for latest dpll init API call] Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ckPeter Ujfalusi2014-06-061-0/+6
| | | | | | | | | | | | | | | | In order to get correct clock dividers for AESS/ABE we need to set the dpll_abe_m2x2_ck rate to be double of dpll_abe_ck. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)Peter Ujfalusi2014-05-282-1/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Audio Tracking Logic is designed to be used by HD Radio applications to synchronize the audio output clocks to the baseband clock. ATL can be also used to track errors between two reference clocks (BWS, AWS) and generate a modulated clock output which averages to some desired frequency. In essence ATL is generating a clock to be used by an audio codec and also to be used by the SoC as MCLK. To be able to integrate the ATL provided clocks to the clock tree we need two types of DT binding: - DT clock nodes to represent the ATL clocks towards the CCF - binding for the ATL IP itself which is going to handle the hw configuration The reason for this type of setup is that ATL itself is a separate device in the SoC, it has it's own address space and clock domain. Other IPs can use the ATL generated clock as their functional clock (McASPs for example) and external components like audio codecs can also use the very same clock as their MCLK. The ATL IP in DRA7 contains 4 ATL instences. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clockPeter Ujfalusi2014-05-281-1/+1
| | | | | | | | | | | | | | | | To allign the name with the other atl clock names: atlclkin3_ck -> atl_clkin3_ck Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: gate: add composite interface clock to OMAP2 only buildTero Kristo2014-05-281-1/+1
| | | | | | | | | | | | | | Composite interface clock is needed by OMAP2, but it was only built in for OMAP3. Fixed the conditional build flag checks for this. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * ARM: OMAP2: clock: add DT boot support for cpufreq_ckTero Kristo2014-05-281-0/+2
| | | | | | | | | | | | The clock and clkdev for this are added manually. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: OMAP2: add clock init supportTero Kristo2014-05-282-0/+255
| | | | | | | | | | | | | | Adds support for registering the alias clocks, boot time clock-enable list and disabling autoidle of clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: interface: add support for omap2430 specific interface clockTero Kristo2014-05-281-0/+11
| | | | | | | | | | | | | | OMAP2430 I2CHS modules require specific hardware ops to be used, so added a new compatible string for this. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: APLL: add support for omap2 apllsTero Kristo2014-05-281-0/+181
| | | | | | | | | | | | | | This patch adds support for omap2 type aplls, which have gating and autoidle functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: DPLL: add support for omap2 core dpllTero Kristo2014-05-281-11/+67
| | | | | | | | | | | | | | | | OMAP2 has slightly different DPLL compared to later OMAP generations. This patch adds support for the ti,omap2-dpll-core-clock and also adds the bindings documentation. Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * CLK: TI: DPLL: simplify autoidle register detection logicTero Kristo2014-05-281-24/+15Star
| | | | | | | | | | | | | | | | | | AMxxxx dpll_data previously had autoidle_mask set, even if these SoC:s don't have autoidle register. Remove the bit-field value as it is unused, also drop the unnecessary DPLL_HAS_AUTOIDLE flag passing during init, as we can just simply check against the contents of the autoidle_mask. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | Merge tag 'clk-for-linus-3.16' of ↵Linus Torvalds2014-06-0864-756/+5469
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux into next Pull clock framework updates from Mike Turquette: "The clock framework changes for 3.16 are pretty typical: mostly clock driver additions and fixes. There are additions to the clock core code for some of the basic types (e.g. the common divider type has some fixes and featured added to it). One minor annoyance is a last-minute dependency that wasn't handled quite right. Commit ba0fae3b06a6 ("clk: berlin: add core clock driver for BG2/BG2CD") in this pull request depends on include/dt-bindings/clock/berlin2.h, which is already in your tree via the arm-soc pull request. Building for the berlin platform will break when the clk tree is built on it's own, but merged into your master branch everything should be fine" * tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits) mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs clk: export __clk_round_rate for providers clk: versatile: free icst on error return clk: qcom: Return error pointers for unimplemented clocks clk: qcom: Support msm8974pro global clock control hardware clk: qcom: Properly support display clocks on msm8974 clk: qcom: Support display RCG clocks clk: qcom: Return highest rate when round_rate() exceeds plan clk: qcom: Fix mmcc-8974's PLL configurations clk: qcom: Fix clk_rcg2_is_enabled() check clk: berlin: add core clock driver for BG2Q clk: berlin: add core clock driver for BG2/BG2CD clk: berlin: add driver for BG2x complex divider cells clk: berlin: add driver for BG2x simple PLLs clk: berlin: add driver for BG2x audio/video PLL clk: st: Terminate of match table clk/exynos4: Fix compilation warning ARM: shmobile: r8a7779: Add clock index macros for DT sources clk: divider: Fix overflow in clk_divider_bestdiv clk: u300: Terminate of match table ...
| * | clk: export __clk_round_rate for providersArnd Bergmann2014-06-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 99cbd064b0 ("clk: qcom: Support display RCG clocks") adds a use of the __clk_round_rate in a clock provided that can be built as a loadable module. This exports the symbol to avoid the build error from compiling the qcom clock as a module. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: versatile: free icst on error returnColin Ian King2014-05-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | commit a183da63 introduced a new error return path that does not kfree icst if the kmemdup of desc->params fails. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Return error pointers for unimplemented clocksStephen Boyd2014-05-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all clocks are implemented but client drivers can still request them. Currently we will return a NULL pointer to them if the clock isn't implemented in software but NULL pointers are valid clock pointers. Return an error pointer so that driver's don't proceed without a clock they may actually need. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Support msm8974pro global clock control hardwareStephen Boyd2014-05-291-6/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | A new PLL (gpll4) is added on msm8974 PRO devices to support a faster sdc1 clock rate. Add support for this and the two new sdcc cal clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Properly support display clocks on msm8974Stephen Boyd2014-05-291-51/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The display clocks all source from dedicated phy PLLs within their respective multimedia hardware block. Hook up these PLLs to the display clocks with the appropriate parent mappings, clock flags, and the appropriate clock ops. This should allow the display clocks to work once the appropriate phy PLL driver registers their PLL clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Support display RCG clocksStephen Boyd2014-05-292-15/+287
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Return highest rate when round_rate() exceeds planStephen Boyd2014-05-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers may want to call clk_set_rate() with a very large number to force the clock to go as fast as it possibly can without having to know the range between the highest rate and second highest rate. Add support for this by defaulting to the highest rate in the frequency table if we can't find a frequency greater than what is requested. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Fix mmcc-8974's PLL configurationsStephen Boyd2014-05-291-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We forgot to add the status bit for the PLLs and we were using the wrong register and masks for configuration, leading to unexpected PLL configurations. Fix this. Fixes: d8b212014e69 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: qcom: Fix clk_rcg2_is_enabled() checkStephen Boyd2014-05-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the bit is set the clock is off so we should be checking for a clear bit, not a set bit. Invert the logic. Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: berlin: add core clock driver for BG2QAlexandre Belloni2014-05-292-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver deals with the core clocks found on Marvell Berlin BG2Q. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: berlin: add core clock driver for BG2/BG2CDSebastian Hesselbarth2014-05-293-0/+722
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver deals with the core clocks found on Marvell Berlin BG2 and BG2CD. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: berlin: add driver for BG2x complex divider cellsAlexandre Belloni2014-05-293-1/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for the complex divider cells found on Marvell Berlin2 SoCs. The cells come in two flavors: single register cells and shared register cells. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: berlin: add driver for BG2x simple PLLsAlexandre Belloni2014-05-293-1/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: berlin: add driver for BG2x audio/video PLLSebastian Hesselbarth2014-05-294-0/+431
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a driver for the AVPLLs built upon a VCO with 8 channels each found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share the same register set, sometimes registers shifts for one of the VCOs are a bit off. Nothing serious that should require a separate driver, so deal with both VCOs in a single driver instead. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk: st: Terminate of match tableStephen Boyd2014-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | clk/exynos4: Fix compilation warningSachin Kamat2014-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following warning: WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown) The function exynos4_clk_sleep_init() references the (unknown reference) __initdata (unknown). This is often because exynos4_clk_sleep_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-282-22/+46
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| * | | clk: divider: Fix overflow in clk_divider_bestdivTomasz Figa2014-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c686078 ("clk: divider: Add round to closest divider") introduced a helper function to check whether given divisor is the best one instead of direct check. However due to int type used instead of unsigned long for passing calculated rates to this function in certain cases an overflow could occur, for example when trying to obtain maximum possible clock rate by calling clk_round_rate(..., UINT_MAX). This patch fixes this issue by changing the type of rate, now and best arguments of the function to unsigned long, which is the type that should be used for clock rates. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: u300: Terminate of match tableStephen Boyd2014-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: bcm/kona: implement determine_rate()Alex Elder2014-05-281-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the clk->determine_rate method for Broadcom Kona peripheral clocks. This allows a peripheral clock to be re-parented in order to satisfy a rate change request. This takes the place of the previous kona_peri_clk_round_rate() functionality, though that function remains because it is used by the new one. The parent clock that allows the peripheral clock to produce a rate closest to the one requested is the one selected, though the current parent is used by default. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: qcom: Fix blsp2_ahb_clk register offsetGeorgi Djakov2014-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The address of the blsp2_ahb_clk register is incorrect. Fix it. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: s2mps11: Add support for S2MPS14 clocksKrzysztof Kozlowski2014-05-242-20/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the s2mps11 clock driver. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: s2mps11: Remove useless check for clk_tableKrzysztof Kozlowski2014-05-241-13/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need for checking if 'clk_table' is not NULL twice (first after allocation and second at the end of probe()). Also move allocation of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is logical place for it. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: s2mps11: Add missing of_node_put and of_clk_del_providerKrzysztof Kozlowski2014-05-241-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add of_clk_del_provider to remove previously registered clock provider. Add of_node_put to decrement the ref count of clock nodes. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-231-1/+1
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| * \ \ \ Merge remote-tracking branch 'linaro/clk-next' into clk-nextMike Turquette2014-05-2347-644/+2815
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| | * | | | clk: Neaten clk_summary outputGeert Uytterhoeven2014-05-231-4/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Limit ruler to 80 characters (was: 81), - Widen rate column by 1 for nicer spacing, - Right-align numbers and their column headers, - Move a newline to reduce the number of seq_printf() calls, - Use set_puts() for fixed strings. Before: clock enable_cnt prepare_cnt rate accuracy --------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 After: clock enable_cnt prepare_cnt rate accuracy -------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| | * | | | clk: divider: add CLK_DIVIDER_READ_ONLY flagHeiko Stuebner2014-05-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by: Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Max Schwarz <max.schwarz@online.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| | * | | | clk: shmobile: Add R8A7740-specific clock supportUlrich Hecht2014-05-232-0/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-18 18:21:00 +0200