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| | | | * | clk: imx7d: add IMX7D_MU_ROOT_CLKOleksij Rempel2018-07-091-0/+1
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is needed for iMX mailbox driver Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * | clk: meson: add gen_clkJerome Brunet2018-07-094-3/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet2018-07-091-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | clk: meson-axg: add clocks required by pcie driverYixun Lan2018-07-092-1/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding clocks for the pcie driver. Due to the ASIC design, the pcie controller re-use part of the mipi clock logic, so the mipi clock is also added. Tested-by: Jianxin Qin <jianxin.qin@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> [amended to remove unnecessary locales] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | clk: meson: remove unused clk-audio-divider driverJerome Brunet2018-07-093-119/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-audio-divider is no longer used, we can remove it. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is actually a lot easier to setup the PLL with carefully chosen rates than relying on CCF clock propagation for this audio use case. This way, we can make sure we will always be able to provide the common audio clock rates, while having the PLL in the optimal operating range. For this, we stop the rate propagation at the mux picking the PLL and let it round to the closest matching PLL. Doing so, we can use the generic divider for the i2s clock. clk-audio-divider is no longer required. It was a (poor) attempt to use CCF rate propagation while making sure the PLL rate would be high enough to work with audio use cases. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | clk: meson: axg: add the audio clock controller driverJerome Brunet2018-07-094-0/+982
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | clk: meson: add axg audio sclk divider driverJerome Brunet2018-07-093-1/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | Merge remote-tracking branch 'clk/clk-core-duty-cycle' into next/driversJerome Brunet2018-07-091-5/+194
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| | | * | | clk: meson: add triple phase clock driverJerome Brunet2018-07-094-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | | clk: meson: add clk-phase clock driverJerome Brunet2018-07-093-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | | clk: meson: clean-up meson clock configurationJerome Brunet2018-07-091-9/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | | * | | clk: meson: remove obsolete register accessJerome Brunet2018-07-092-69/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The legacy method to access the hhi register space is not longer used. We can safely drop it now. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | clk: mvebu: armada-37xx-periph: switch to SPDX license identifierGregory CLEMENT2018-07-091-4/+1Star
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-------. \ \ \ Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', ↵Stephen Boyd2018-08-155-36/+30Star
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next * clk-imx-critical: : - Convert to CLK_IS_CRITICAL for i.MX51/53 driver clk: imx51-imx53: Include sizes.h to silence compile errors clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL * clk-tegra-bpmp: : - Fix Tegra BPMP driver oops when some xlating a NULL clk clk: tegra: bpmp: Don't crash when a clock fails to register * clk-tegra-124: : - Proper default configuration for vic03 and vde clks on Tegra124 clk: tegra: Make vde a child of pll_c3 clk: tegra: Make vic03 a child of pll_c3 * clk-tegra-critical: : - Mark Tegra memory controller clks as critical clk: tegra: Mark Memory Controller clock as critical * clk-tegra-emc-oob: : - Fix array bounds clamp in Tegra's emc determine_rate() op clk: tegra: emc: Avoid out-of-bounds bug
| | | | | | * | | | clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko2018-07-091-1/+1
| | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently there was an attempt to avoid out-of-bounds accesses when there is only one memory timing available, but there is a typo in the code that neglects that attempt. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * / / / clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko2018-07-091-2/+3
| | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory Controller should be always-on. Currently the sibling EMC clock is marked as critical, let's mark MC clock too for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | | | clk: tegra: Make vde a child of pll_c3Thierry Reding2018-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | | | clk: tegra: Make vic03 a child of pll_c3Thierry Reding2018-07-091-0/+1
| | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * / / / clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen2018-07-091-3/+9
| | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When registering clocks, we just skip any that fail to register (leaving a NULL hole in the clock table). However, our of_xlate function still tries to dereference each entry while looking for the clock with the requested id, causing a crash if any clocks failed to register. Add a check to of_xlate to skip any NULL clocks. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | | | clk: imx51-imx53: Include sizes.h to silence compile errorsStephen Boyd2018-07-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver uses sizes.h, but relies on it being implicitly included somewhere else breaking random direct compilation of the file. Include sizes.h so we can build it those configurations too for better compile coverage. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | | | clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICALFabio Estevam2018-07-061-29/+14Star
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of explicitly enabling critical clocks via clk_prepare_enable(), let's use the standard CLK_IS_CRITICAL flag instead, which makes the code a bit shorter. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-------. \ \ \ Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', ↵Stephen Boyd2018-08-159-11/+415
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next * clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs
| | | | | | * | | | clk: imx6sll: add GPIO LPCGsAnson Huang2018-07-061-0/+6
| | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs defined in CCM CCGRs, add them into clock tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * / / / clk: aspeed: Fix SDCLK nameLei YU2018-07-061-1/+1
| | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * / / / clk: pxa: export 32kHz PLLRobert Jarzmik2018-07-063-8/+12
| | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | * / / / clk: Add driver for MAX9485Daniel Mack2018-07-063-0/+394
| | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for MAX9485, a programmable audio clock generator. The device requires a 27.000 MHz clock input. It can provide a gated buffered output of its input clock and two gated outputs of a PLL that can generate one out of 16 discrete frequencies. There is only one PLL however, so the two gated outputs will always have the same frequency but they can be switched individually. The driver for this device exposes 4 clocks in total: - MAX9485_MCLKOUT: A gated, buffered output of the input clock - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete frequencies - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT Some PLL output frequencies can be achieved with different register settings. The driver will select the one with lowest jitter in such cases. Signed-off-by: Daniel Mack <daniel@zonque.org> [sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate() and shorten line of max9485_of_clk_get()] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | | | clk: ingenic: Add missing flag for UDC clockPaul Cercueil2018-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | | | clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil2018-07-061-1/+1
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register field for configuring the divider for the i2s clock occupies the bits [8-0], which means 9 bits and not 8. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-------. \ \ \ Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', ↵Stephen Boyd2018-08-159-7/+1066
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next * clk-imx6-video-parent: : - Fix i.MX6QDL video clk parent clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL * clk-qcom-sdm845-criticals: : - critical clk markings for qcom SDM845 clk: qcom: Enable clocks which needs to be always on for SDM845 * clk-renesas: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock * clk-stratix10-fixes: : - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents clk: socfpga: stratix10: fix the sdmmc_free_clk mux clk: socfpga: stratix10: fix the parents of mpu_free_clk * clk-atmel-i2s: : - Atmel at91 I2S audio clk support clk: at91: add I2S clock mux driver dt-bindings: clk: at91: add an I2S mux clock
| | | | | | * | | | clk: at91: add I2S clock mux driverCodrin Ciubotariu2018-07-062-0/+117
| | | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is a simple muxing driver that controls the I2S's clock input by using syscon/regmap to change the parent. The available inputs can be peripheral clock and generated clock. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> [sboyd@kernel.org: Fix SPDX tag comment style] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * | | | clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen2018-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first parent of the sdmmc_free_clk should be the main_sdmmc_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * | | | clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen2018-07-061-1/+6
| | | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a clock mux that is used as a parent for the mpu_free_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * | | | clk: renesas: Renesas R9A06G032 clock driverMichel Pollet2018-06-253-0/+900
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a clock driver for the Renesas R09A06G032. This uses a structure derived from both the R-Car Gen2 driver as well as the renesas-cpg-mssr driver. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | | | * | | | clk: renesas: r8a7795: Add CCREE clockGilad Ben-Yossef2018-06-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the clock used by the CryptoCell 630p instance in the SoC. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | | | * | | | clk: renesas: r8a7795: Add CR clockGeert Uytterhoeven2018-06-191-0/+1
| | | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the CR core clock, which is used by the Secure Engine (SCEG). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
| | | * / / / clk: qcom: Enable clocks which needs to be always on for SDM845Amit Nischal2018-07-031-4/+39
| | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are certain clocks which needs to be always enabled for system operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag for such clocks. Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * / / / clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SELPhilipp Puschmann2018-06-291-1/+1
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | q/dl datasheets list the 5th selection value for ck01_sel as video_27M_clk_root. By replacing the dummy value we then can set IMX6QDL_CLK_VIDEO_27M as parent for IMX6QDL_CLK_CKO1_SEL. Signed-off-by: Philipp Puschmann <pp@emlix.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *-----. \ \ \ Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', ↵Stephen Boyd2018-08-154-27/+292
| |\ \ \ \ \ \ \ | | | | |_|_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-core-duty-cycle', 'clk-si-prepare' and 'clk-imx-gpio-gates' into clk-next * clk-qcom-set-rate-gate: clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks * clk-core-set-rate-gate: clk: fix CLK_SET_RATE_GATE with clock rate protection * clk-core-duty-cycle: clk: add duty cycle support * clk-si-prepare: : - SI544/SI514 clk on/off support clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations * clk-imx-gpio-gates: : - i.MX6UL GPIO clock gates in CCM CCGR clk: imx6ul: remove clks_init_on array clk: imx6ul: add GPIO clock gates dt-bindings: clock: imx6ul: Do not change the clock definition order
| | | | | * | | clk: imx6ul: remove clks_init_on arrayAnson Huang2018-06-291-17/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. ARM clock is busy divider type which has the CLK_IS_CRITICAL flag set by default when registered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | | * | | clk: imx6ul: add GPIO clock gatesAnson Huang2018-06-291-0/+5
| | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX6UL has GPIO clock gates in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | | | * / / clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operationsMike Looijmans2018-06-292-2/+74
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds prepare/unprepare/is_prepared functionality to the drivers for the SI544 and SI514 chips, allowing the clock output to be disabled when the clock is not in use. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * | / / clk: fix CLK_SET_RATE_GATE with clock rate protectionJerome Brunet2018-06-191-3/+13
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CLK_SET_RATE_GATE should prevent any operation which may result in a rate change or glitch while the clock is prepared/enabled. IOW, the following sequence is not allowed anymore with CLK_SET_RATE_GATE: * clk_get() * clk_prepare_enable() * clk_get_rate() * clk_set_rate() At the moment this is enforced on the leaf clock of the operation, not along the tree. This problematic because, if a PLL has the CLK_RATE_GATE, it won't be enforced if the clk_set_rate() is called on its child clocks. Using clock rate protection, we can now enforce CLK_SET_RATE_GATE along the clock tree Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180619134051.16726-3-jbrunet@baylibre.com
| * / | | clk: qcom: drop CLK_SET_RATE_GATE from sdc clocksJerome Brunet2018-06-194-15/+0Star
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the mmci driver (drivers/mmc/host/mmci.c) does the following sequence: * clk_prepare_enable() * clk_set_rate() on SDCx_clk which is a children of SDCx_src. SDCx_src has CLK_SET_RATE_GATE so this sequence should not be allowed but this was not enforced. IOW, the flag is ignored. Dropping the flag won't change anything to the current behaviour of the platform. CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept, the mmci driver would receive -EBUSY when calling clk_set_rate() Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180619134051.16726-2-jbrunet@baylibre.com
* | | | Merge tag 'sound-4.19-rc1' of ↵Linus Torvalds2018-08-141-5/+194
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound updates from Takashi Iwai: "It's been busy summer weeks and hence lots of changes, partly for a few new drivers and partly for a wide range of fixes. Here are highlights: ALSA Core: - Fix rawmidi buffer management, code cleanup / refactoring - Fix the SG-buffer page handling with incorrect fallback size - Fix the stall at virmidi trigger callback with a large buffer; also offloading and code-refactoring along with it - Various ALSA sequencer code cleanups ASoC: - Deploy the standard snd_pcm_stop_xrun() helper in several drivers - Support for providing name prefixes to generic component nodes - Quite a few fixes for DPCM as it gains a bit wider use and more robust testing - Generalization of the DIO2125 support to a simple amplifier driver - Accessory detection support for the audio graph card - DT support for PXA AC'97 devices - Quirks for a number of new x86 systems - Support for AM Logic Meson, Everest ES7154, Intel systems with RT5682, Qualcomm QDSP6 and WCD9335, Realtek RT5682 and TI TAS5707 HD-audio: - Code refactoring in HD-audio ext codec codes to drop own classes; preliminary works for the upcoming legacy codec support - Generalized DRM audio component for the upcoming radeon / amdgpu support - Unification of mic mute-LED and GPIO support for various codecs - Further improvement of CA0132 codec support including Recon3D - Proper vga_switcheroo handling for AMD i-GPU - Update of model list in documentation - Fixups for another HP Spectre x360, Conexant codecs, power-save blacklist update USB-audio: - Fix the invalid sample rate setup with external clock - Support of UAC3 selector units and processing units - Basic UAC3 power-domain support - Support for Encore mDSD and Thesycon-based DSD devices - Preparation for future complete callback changes Firewire: - Add support for MOTU Traveler Misc: - The endianess notation fixes in various drivers - Add fall-through comment in lots of drivers - Various sparse warning fixes, e.g. about PCM format types" * tag 'sound-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (529 commits) ASoC: adav80x: mark expected switch fall-through ASoC: da7219: Add delays to capture path to remove DC offset noise ALSA: usb-audio: Mark expected switch fall-through ALSA: mixart: Mark expected switch fall-through ALSA: opl3: Mark expected switch fall-through ALSA: hda/ca0132 - Add exit commands for Recon3D ALSA: hda/ca0132 - Change mixer controls for Recon3D ALSA: hda/ca0132 - Add Recon3D input and output select commands ALSA: hda/ca0132 - Add DSP setup defaults for Recon3D ALSA: hda/ca0132 - Add Recon3D startup functions and setup ALSA: hda/ca0132 - Add bool variable to enable/disable pci region2 mmio ALSA: hda/ca0132 - Add Recon3D pincfg ALSA: hda/ca0132 - Add quirk ID and enum for Recon3D ALSA: hda/ca0132 - Add alt_functions unsolicited response ALSA: hda/ca0132 - Clean up ca0132_init function. ALSA: hda/ca0132 - Create mmio gpio function to make code clearer ASoC: wm_adsp: Make DSP name configurable by codec driver ASoC: wm_adsp: Declare firmware controls from codec driver ASoC: max98373: Added software reset register to readable registers ASoC: wm_adsp: Correct DSP pointer for preloader control ...
| * \ \ \ Merge branch 'asoc-4.19' into asoc-nextMark Brown2018-08-091-5/+194
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| | * | | clk: add duty cycle supportJerome Brunet2018-06-191-5/+194
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the possibility to apply and query the clock signal duty cycle ratio. This is useful when the duty cycle of the clock signal depends on some other parameters controlled by the clock framework. For example, the duty cycle of a divider may depends on the raw divider setting (ratio = N / div) , which is controlled by the CCF. In such case, going through the pwm framework to control the duty cycle ratio of this clock would be a burden. A clock provider is not required to implement the operation to set and get the duty cycle. If it does not implement .get_duty_cycle(), the ratio is assumed to be 50%. This change also adds a new flag, CLK_DUTY_CYCLE_PARENT. This flag should be used to indicate that a clock, such as gates and muxes, may inherit the duty cycle ratio of its parent clock. If a clock does not provide a get_duty_cycle() callback and has CLK_DUTY_CYCLE_PARENT, then the call will be directly forwarded to its parent clock, if any. For set_duty_cycle(), the clock should also have CLK_SET_RATE_PARENT for the call to be forwarded Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20180619144141.8506-1-jbrunet@baylibre.com
* | | | Merge branch 'clkdev' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds2018-08-141-4/+1Star
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM clkdev updates from Russell King: "A couple of cleanups for clkdev" * 'clkdev' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8778/1: clkdev: don't call __of_clk_get_by_name() unnecessarily from clk_get() ARM: 8776/1: clkdev: Remove duplicated negative index check from __of_clk_get()
| * | | ARM: 8778/1: clkdev: don't call __of_clk_get_by_name() unnecessarily from ↵Bartosz Golaszewski2018-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_get() The way this function is implemented caused some confusion when converting the TI DaVinci platform to using the common clock framework. Current kernel supports booting DaVinci boards both in device tree as well as legacy, board-file mode. In the latter, we always end up calling clk_get_sys() as of_node is NULL and __of_clk_get_by_name() returns -ENOENT. It was not obvious at first glance how clk_get(dev, NULL) will work in board-file mode since we always call __of_clk_get_by_name(). Let's make it clearer by checking if of_node is NULL and skipping right to clk_get_sys(). Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: David Lechner <david@lechnology.com> Reviewed-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
| * | | ARM: 8776/1: clkdev: Remove duplicated negative index check from __of_clk_get()Geert Uytterhoeven2018-07-111-3/+0Star
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | __of_clk_get() calls of_parse_phandle_with_args(), which rejects negative indices since commit bd69f73f2c81eed9 ("of: Create function for counting number of phandles in a property"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-15 00:42:07 +0200