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* Merge tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2015-09-0448-5168/+7606
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This time we have aded a new capability for scatter-gathered memset using dmaengine APIs. This is supported in xdmac & hdmac drivers We have added support for reusing descriptors for examples like video buffers etc. Driver will follow The behaviour of descriptor ack has been clarified and documented New devices added are: - dma controller in sun[457]i SoCs - lpc18xx dmamux - ZTE ZX296702 dma controller - Analog Devices AXI-DMAC DMA controller - eDMA support for dma-crossbar - imx6sx support in imx-sdma driver - imx-sdma device to device support Other: - jz4780 fixes - ioatdma large refactor and cleanup for removal of ioat v1 and v2 which is deprecated and fixes - ACPI support in X-Gene DMA engine driver - ipu irq fixes - mvxor fixes - minor fixes spread thru drivers" [ The Kconfig and Makefile entries got re-sorted alphabetically, and I handled the conflict with the new Intel integrated IDMA driver by slightly mis-sorting it on purpose: "IDMA64" got sorted after "IMX" in order to keep the Intel entries together. I think it might be a good idea to just rename the IDMA64 config entry to INTEL_IDMA64 to make the sorting be a true sort, not this mismash. Also, this merge disables the COMPILE_TEST for the sun4i DMA controller, because it does not compile cleanly at all. - Linus ] * tag 'dmaengine-4.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits) dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDs dmaengine :ipu: change ipu_irq_handler() to remove compile warning dmaengine: ioatdma: Fix variable array length dmaengine: ioatdma: fix sparse "error" with prep lock dmaengine: hdmac: Add memset capabilities dmaengine: sort the sh Makefile dmaengine: sort the sh Kconfig dmaengine: sort the dw Kconfig dmaengine: sort the Kconfig dmaengine: sort the makefile drivers/dma: make mv_xor.c driver explicitly non-modular dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller devicetree: Add bindings documentation for Analog Devices AXI-DMAC dmaengine: xgene-dma: Fix the lock to allow client for further submission of requests dmaengine: ioatdma: fix coccinelle warning dmaengine: ioatdma: fix zero day warning on incompatible pointer type dmaengine: tegra-apb: Simplify locking for device using global pause dmaengine: tegra-apb: Remove unnecessary return statements and variables dmaengine: tegra-apb: Avoid unnecessary channel base address calculation dmaengine: tegra-apb: Remove unused variables ...
| * dmaengine: ioatdma: add Broadwell EP ioatdma PCI dev IDsDave Jiang2015-08-282-1/+42
| | | | | | | | | | | | | | | | Adding the Broadwell Xeon ioatdma PCI device IDs and related bits. This is still IOATDMA 3.2 based hw. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine :ipu: change ipu_irq_handler() to remove compile warningyalin wang2015-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | Change ipu_irq_handler() to avoid gcc warning: drivers/dma/ipu/ipu_irq.c:305:4: warning: 'irq' may be used uninitialized in this function [-Wmaybe-uninitialized] generic_handle_irq(irq); Signed-off-by: yalin wang <yalin.wang2010@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: ioatdma: Fix variable array lengthDave Jiang2015-08-261-2/+10
| | | | | | | | | | | | | | | | | | | | Sparse reported: drivers/dma/ioat/prep.c:637:27: sparse: Variable length array is used. Assigning a static value for the array. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: ioatdma: fix sparse "error" with prep lockDave Jiang2015-08-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | The prep lock gets acquired in ioat_check_space_lock and released in ioat_tx_submit_unlock. Setting the annotations so sparse does not freak out. drivers/dma/ioat/dma.c:273:30: sparse: context imbalance in 'ioat_tx_submit_unlock' - unexpected unlock drivers/dma/ioat/dma.c:476:5: sparse: context imbalance in 'ioat_check_space_lock' - wrong count at exit Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: hdmac: Add memset capabilitiesMaxime Ripard2015-08-262-3/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | Just like for the XDMAC, the SoCs that embed the HDMAC don't have any kind of GPU, and need to accelerate a few framebuffer-related operations through their DMA controller. However, unlike the XDMAC, the HDMAC doesn't have the memset capability built-in. That can be easily emulated though, by doing a transfer with a fixed address on the variable that holds the value we want to set. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sort the sh MakefileVinod Koul2015-08-261-2/+2
| | | | | | | | | | Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sort the sh KconfigVinod Koul2015-08-261-12/+12
| | | | | | | | | | Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sort the dw KconfigVinod Koul2015-08-241-3/+3
| | | | | | | | Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sort the KconfigVinod Koul2015-08-241-310/+316
| | | | | | | | | | | | | | | | dmaengine Kconfig grew over the years, unfortunately without any order to it. So order by core, driver and client sections, and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sort the makefileVinod Koul2015-08-241-41/+47
| | | | | | | | | | | | | | | | dmaengine makefile grew over the years, unfortunately without any order to it. So order by core, dmatest and driver sections and sort these sections alphabetically Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * drivers/dma: make mv_xor.c driver explicitly non-modularPaul Gortmaker2015-08-231-33/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig for this driver is currently: config MV_XOR bool "Marvell XOR engine support" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We leave some tags like MODULE_AUTHOR for documentation purposes. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: Add support for the Analog Devices AXI-DMAC DMA controllerLars-Peter Clausen2015-08-233-0/+702
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Analog Devices AXI-DMAC DMA controller. This controller is a soft peripheral that can be instantiated in a FPGA and is often used in Analog Devices' reference designs for FPGA platforms. The peripheral has various configuration options that can be selected at synthesis time and influence the supported features of the instantiated peripheral, those options are represented as device-tree properties to allow the driver to behave accordingly. The peripheral has a zero latency architecture, which means it is possible to switch from one to the next descriptor without any delay. This is archived by having a internal queue which can hold multiple descriptors. The driver supports this, which means it will submit new descriptors directly to the hardware until the queue is full and not wait for a descriptor to complete before the next one is submitted. Interrupts are used for the descriptor queue flow control. Currently the driver supports SG, cyclic and interleaved slave DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * Merge branch 'topic/zxdma' into for-linusVinod Koul2015-08-233-0/+959
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| | * dmaengine: zxdma: Fix force stop bugJun Nie2015-08-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | DMA will not stop when clearing enable bit till all transaction is done. The bug is exposed in audio playback because ring DMA chain never stop. Force hardware to stop with setting FORCE bit. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dmaengine: zxdma: Fix data width bugJun Nie2015-08-051-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align src and dst width to fix data alignment issue as trailing single transaction that does not fill a full burst require identical src/dst data width. Burst length limitation can be addressed well too. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dmaengine: zxdma: Support cyclic dmaJun Nie2015-08-051-9/+84
| | | | | | | | | | | | | | | | | | | | | Support cyclic dma for audio playback Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dmaengine: zxdma: explicitly free irq on device removalVinod Koul2015-07-161-3/+7
| | | | | | | | | | | | | | | | | | | | | At device removal, tasklets are not disabled and irqs are still enabled, so free the irq explicitly on device removal Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dmaengine: zxdma: Support ZTE ZX296702 dmaJun Nie2015-07-163-0/+878
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add ZTE ZX296702 dma controller support. Only device tree probe is support currently. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/ti-xbar' into for-linusVinod Koul2015-08-231-10/+31
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| | * | dmaengine: ti-dma-crossbar: Fix checking return value of devm_ioremap_resourceAxel Lin2015-08-051-5/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_ioremap_resource returns ERR_PTR on failure. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: ti-dma-crossbar: Add support for eDMAPeter Ujfalusi2015-07-221-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The crossbar for eDMA works exactly the same way as sDMA, but sDMA requires an offset of 1, while no offset is needed for eDMA. Based on the patch from Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> CC: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: ti-dma-crossbar: Make idr xbar instance-specificMisael Lopez Cruz2015-07-221-4/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | In preparation for supporting multiple DMA crossbar instances, make the idr xbar instance specific. Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/at_xdmac' into for-linusVinod Koul2015-08-231-6/+6
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| | * | dmaengine: at_xdmac: fix indentationLudovic Desroches2015-07-061-6/+6
| | |/ | | | | | | | | | | | | | | | | | | Fix indentation. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: xgene-dma: Fix the lock to allow client for further submission of ↵Rameshwar Prasad Sahu2015-08-211-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | requests This patch provides the fix in the cleanup routing such that client can perform further submission by releasing the lock before calling client's callback function. Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: ioatdma: fix coccinelle warningDave Jiang2015-08-211-4/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplifying the end return. This existed in the original code but was flagged when refactoring of the code made it appear it's new. coccinelle warnings: (new ones prefixed by >>) >> drivers/dma/ioat/init.c:1018:1-3: WARNING: end returns can be simpified Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: ioatdma: fix zero day warning on incompatible pointer typeDave Jiang2015-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 32bit build is creating this warning. Since we don't expect anyone actually use this on 32bit, restrict ioatdma to be built only on x86_64. This issue has long existed and only reason it's surfacing due to code refactoring. drivers/dma/ioat/dma.c: In function 'ioat_timer_event': >> drivers/dma/ioat/dma.c:870:39: warning: passing argument 2 of 'ioat_cleanup_preamble' from incompatible pointer type if (ioat_cleanup_preamble(ioat_chan, &phys_complete)) ^ drivers/dma/ioat/dma.c:577:13: note: expected 'u64 *' but argument is of type 'dma_addr_t *' static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan, ^ Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: tegra-apb: Simplify locking for device using global pauseJon Hunter2015-08-201-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse reports the following with regard to locking in the tegra_dma_global_pause() and tegra_dma_global_resume() functions: drivers/dma/tegra20-apb-dma.c:362:9: warning: context imbalance in 'tegra_dma_global_pause' - wrong count at exit drivers/dma/tegra20-apb-dma.c:366:13: warning: context imbalance in 'tegra_dma_global_resume' - unexpected unlock The warning is caused because tegra_dma_global_pause() acquires a lock but does not release it. However, the lock is released by tegra_dma_global_resume(). These pause/resume functions are called in pairs and so it does appear to work. This global pause is used on early tegra devices that do not have an individual pause for each channel. The lock appears to be used to ensure that multiple channels do not attempt to assert/de-assert the global pause at the same time which could cause the DMA controller to be in the wrong paused state. Rather than locking around the entire code between the pause and resume, employ a simple counter to keep track of the global pause requests. By using a counter, it is only necessary to hold the lock when pausing and unpausing the DMA controller and hence, fixes the sparse warning. Please note that for devices that support individual channel pausing, the DMA controller lock is not held between pausing and unpausing the channel. Hence, this change will make the devices that use the global pause behave in the same way, with regard to locking, as those that don't. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: tegra-apb: Remove unnecessary return statements and variablesJon Hunter2015-08-201-12/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some void functions have unnecessary return statements at the end (reported by sparse) and so remove these. Also remove the return variables from functions tegra_dma_prep_slave_sg() and tegra_dma_prep_slave_cyclic() because the value is not used. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: tegra-apb: Avoid unnecessary channel base address calculationJon Hunter2015-08-201-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Everytime a DMA channel register is accessed, the channel base address is calculated by adding the DMA base address and the channel register offset. Avoid this calculation and simply calculate the channel base address once at probe time for each DMA channel. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: tegra-apb: Remove unused variablesJon Hunter2015-08-201-4/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The callback and callback_param members of the tegra_dma_sg_req structure are never used. The dma-engine structure, dma_async_tx_descriptor, defines the same members and these are the ones used by the driver. Therefore, remove the unused versions from the tegra_dma_sg_req structure. The half_done member of tegra_dma_channel structure is configured but never used and so remove it. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: xgene-dma: Add ACPI support for X-Gene DMA engine driverRameshwar Prasad Sahu2015-08-201-7/+21
| | | | | | | | | | | | | | | | | | | | | This patch adds ACPI support for the APM X-Gene DMA engine driver. Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: imx-sdma: Check for clk_enable() errorsFabio Estevam2015-08-201-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | clk_enable() may fail, so we should better check the return value and propagate it in the case of error. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: sun4i: Add support for the DMA engine on sun[457]i SoCsEmilio López2015-08-203-0/+1300
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DMA engine present on Allwinner A10, A13, A10S and A20 SoCs. This engine has two kinds of channels: normal and dedicated. The main difference is in the mode of operation; while a single normal channel may be operating at any given time, dedicated channels may operate simultaneously provided there is no overlap of source or destination. Hardware documentation can be found on A10 User Manual (section 12), A13 User Manual (section 14) and A20 User Manual (section 1.12) Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: mv_xor: optimize performance by using a subset of the XOR channelsThomas Petazzoni2015-08-191-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to how async_tx behaves internally, having more XOR channels than CPUs is actually hurting performance more than it improves it, because memcpy requests get scheduled on a different channel than the XOR requests, but async_tx will still wait for the completion of the memcpy requests before scheduling the XOR requests. It is in fact more efficient to have at most one channel per CPU, which this patch implements by limiting the number of channels per engine, and the number of engines registered depending on the number of availables CPUs. Marvell platforms are currently available in one CPU, two CPUs and four CPUs configurations: - in the configurations with one CPU, only one channel from one engine is used. - in the configurations with two CPUs, only one channel from each engine is used (they are two XOR engines) - in the configurations with four CPUs, both channels of both engines are used. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: mv_xor: remove support for dmacap,* DT propertiesThomas Petazzoni2015-08-191-6/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only reason why we had dmacap,* properties is because back when DMA_MEMSET was supported, only one out of the two channels per engine could do a memset operation. But this is something that the driver already knows anyway, and since then, the DMA_MEMSET support has been removed. The driver is already well aware of what each channel supports and the one to one mapping between Linux specific implementation details (such as dmacap,interrupt enabling DMA_INTERRUPT) and DT properties is a good indication that these DT properties are wrong. Therefore, this commit simply gets rid of these dmacap,* properties, they are now ignored, and the driver is responsible for knowing the capabilities of the hardware with regard to the dmaengine subsystem expectations. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: pl330: do not emit loop for 1 byte transfer.Michal Suchanek2015-08-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | When there is only one burst required do not emit loop instructions to loop exactly once. Emit just the body of the loop. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: kill off set_irq_flags usageRob Herring2015-08-191-6/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_irq_flags is ARM specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: imx-sdma: Add imx6sx platform supportZidan Wang2015-08-191-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Solo X has more requirements for SDMA events. So it creates a event mux to remap most of event numbers in GPR (General Purpose Register). If we want to use SDMA support for those module who do not get the even number as default, we need to configure GPR first. Thus this patch adds this support of GPR event remapping configuration to the SDMA driver. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: at_xdmac: fix bug in prep_dma_cyclicLudovic Desroches2015-08-191-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In cyclic mode, the round chaining has been broken by the introduction of at_xdmac_queue_desc(): AT_XDMAC_MBR_UBC_NDE is set for all descriptors excepted for the last one. at_xdmac_queue_desc() has to be called one more time to chain the last and the first descriptors. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Fixes: 0d0ee751f7f7 ("dmaengine: xdmac: Rework the chaining logic") Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Kill tasklets before unregistering the deviceAlex Smith2015-08-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tasklets may have been scheduled as a result of an earlier interrupt that could still be running. Kill them before unregistering the device. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Don't use devm_*_irq() functionsAlex Smith2015-08-181-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We must explicitly free the IRQ before the device is unregistered in case any device interrupt still occurs, so there's no point in using the managed variations of the IRQ functions. Change to the regular versions. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Ensure channel is on correct controller in filterAlex Smith2015-08-181-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When scanning for a free DMA channel, the filter function should ensure that the channel is on the controller that it was requested to be on in the DT. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Use dma_get_slave_channel when requesting a specific channelAlex Smith2015-08-181-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the DT requests a specific channel to use it is not necesssary to scan through all DMA channels in the system. Just return the requested channel using dma_get_slave_channel(). Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Fix error handling/signedness issuesAlex Smith2015-08-181-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a some signedness bugs such as testing for < 0 on unsigned return values. Additionally there are some cases where functions which should return NULL on error actually return a PTR_ERR value which can result in oopses on error. Fix these issues. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Fall back on smaller transfer sizes where necessaryAlex Smith2015-08-181-14/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason the controller does not support 8 byte transfers (but does support all other powers of 2 up to 128). In this case fall back to 4 bytes. In addition, fall back to 128 bytes when any larger power of 2 would be possible within the alignment constraints, as this is the maximum supported. It makes no sense to outright reject 8 or >128 bytes just because the alignment constraints make those the maximum possible size given the parameters for the transaction. For instance, this can result in a DMA from/to an 8 byte aligned address failing. It is perfectly safe to fall back to smaller transfer sizes, the only consequence is reduced transfer efficiency, which is far better than not allowing the transfer at all. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: jz4780: Fix up dmaengine API function prototypesAlex Smith2015-08-181-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several function prototypes did not match the dmaengine API they were implementing, resulting in build warnings. Correct these. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Cc: dmaengine@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: sirf: clear pending DMA interrupt when DMA terminatesYanchang Li2015-08-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If DMA interrupt comes and is latched by IRQ controller during the execution of dma_terminate_all(), dma_irq routine will be executed after dma terminated, and it will cause kernel panic. We clear DMA interrupts in dma_terminate_all() to avoid this useless interrupt. Signed-off-by: Yanchang Li <Yanchang.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: add driver for lpc18xx dmamuxJoachim Eastwood2015-08-183-0/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DMA on NXP LPC18xx/43xx platforms which has a multiplexer in front of the PL080 dma request lines. The mux is a single register in the LPC18xx/43xx CREG block and can multiplex up to 4 request lines to each of the 16 lines on the PL080. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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