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path: root/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
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* drm/amd/powerplay:clean up phm_enable_clock_power_gatingsPrike Liang2019-01-141-1/+0Star
| | | | | | | | | As the PG was setted by each IP block durinng IP early init thus remove the unused phm_enable_clock_power_gatings related funcs. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: rv dal-pplib interface refactor powerplay parthersen wu2018-12-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. [HOW] step 1: add new functions at pplib interface step 2: add new functions at amdgpu dm and dc Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: initialize vega20 overdrive settingsEvan Quan2018-08-271-0/+2
| | | | | | | | | The initialized overdrive settings are taken from vbios and SMU( by PPSMC_MSG_TransferTableSmu2Dram). Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Refine the interface exported to displayRex Zhu2018-07-051-1/+1
| | | | | | | | use void * as function parameter type in order for extension. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add a framework for perfroming pre displayEvan Quan2018-05-171-0/+1
| | | | | | | | configuration change settings Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: new framework to honour DAL clock limitsEvan Quan2018-05-171-0/+2
| | | | | | | | | | This is needed for vega12 and vega20 which do not support legacy powerstate. With this new framework, the DAL clocks limits can also be honored on these asics. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Add OVERDRIVE support on Vega10 (v2)Rex Zhu2018-05-151-5/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when bit14 in module parameter ppfeaturemask was set. od feature will be enabled on Vega10 except vbios not support. user can read od range by reading sysfs pp_od_clk_voltage, cat pp_od_clk_voltage OD_SCLK: 0: 852Mhz 800mV 1: 991Mhz 900mV 2: 1138Mhz 950mV 3: 1269Mhz 1000mV 4: 1348Mhz 1050mV 5: 1399Mhz 1100mV 6: 1440Mhz 1150mV 7: 1500Mhz 1200mV OD_MCLK: 0: 167Mhz 800mV 1: 500Mhz 800mV 2: 800Mhz 950mV 3: 945Mhz 1000mV OD_RANGE: SCLK: 852MHz 2200MHz MCLK: 167MHz 1500MHz VDDC: 800mV 1200mV and can configure the clock/voltage by writing pp_od_clk_voltage for example: echo "s 0 900 820">pp_od_clk_voltage to change the sclk/vddc to 900MHz and 820 mV in dpm level0. echo "r" to change the clk/voltage to default value. echo "c">pp_od_clk_voltage to commit the change v2: squash in warning fix (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Refine register_thermal_interrupt functionRex Zhu2018-03-211-1/+1
| | | | | | | | | | | v2: add Vega12 support 1. delete useless argument in function register_thermal_interrupt 2. rename function name register_thermal_interrupt to register_irq_handlers Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add the hw manager for vega12 (v4)Evan Quan2018-03-211-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | handles the driver power state setup v2: squash in the following: - handle negative temperature ranges - add vega12 thermal ranges - use ffs/fls - remove ACG code - resend NumOfDisplays message - correct max dpm levels - remove power containment settings - fix warnings - add sensors interface - delete unused overdrive arbiter - drop get_temperature callback - smu table cleanup - atomfirmware smu dpm table updates v3: rebase v4: rebase Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Revert gfx/compute profile switch sysfsRex Zhu2018-03-061-1/+0Star
| | | | | | | | | | | The gfx/compute profiling mode switch is only for internally test. Not a complete solution and unexpectly upstream. so revert it. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Move DPMTABLE_* definitions to common header fileRex Zhu2018-02-191-0/+11
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Refine code abbreviate variable nameRex Zhu2018-02-191-2/+2
| | | | | | | | | abbreviate variable name number_of_performance_levels to num_of_pl in struct phm_odn_clock_levels Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Refine code shorten variable nameRex Zhu2018-02-191-1/+1
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: remove unused parameter of phm_start_thermal_controller (v2)Evan Quan2018-02-191-1/+1
| | | | | | | | | | Unused. v2: squash in warning fix (Harry) Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: implement phm_reset_power_profile_stateRex Zhu2017-12-191-0/+1
| | | | | | | | | mv related code out of force_dpm_level to phm_reset_power_profile_state Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: fix pcie max lane define errorRex Zhu2017-09-191-1/+1
| | | | | Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: use struct amd_pm_funcs in powerplayRex Zhu2017-09-191-2/+0Star
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Add PP_CAP() macroTom St Denis2017-09-121-0/+2
| | | | | | | | | To replace common lengthy sequence that would create really long lines all over. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: added didt support for vega10Evan Quan2017-07-141-0/+5
| | | | | | Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add disable_smc_ctf callback in hwmgr.Rex Zhu2017-04-281-1/+1
| | | | | | | | | | | | export disablesmcctf to eventmgr. need to disable temperature alert when s3/s4. otherwise, when resume back,enable temperature alert will fail. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add some display/powerplay interfacesEric Huang2017-03-301-0/+11
| | | | | | | | | | | | New interfaces needed to handle the new clock trees and bandwidth requirements on vega10. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add some new structures for Vega10Eric Huang2017-03-301-0/+32
| | | | | | | | Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* scripts/spelling.txt: add "overrided" pattern and fix typo instancesMasahiro Yamada2017-02-281-1/+1
| | | | | | | | | | | Fix typos and add the following to the scripts/spelling.txt: overrided||overridden Link: http://lkml.kernel.org/r/1481573103-11329-22-git-send-email-yamada.masahiro@socionext.com Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* drm/amd/powerplay: disable cg pg task when pp uninitialize.Rex Zhu2016-12-071-0/+1
| | | | | | | | | | fix bug on uvd pg enabled, when reboot vm in pass through case, we need to notify smu power up uvd/vce if they were power down. otherwise, the vbios post will fail. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: initialize platform caps in hwmgr_init.Rex Zhu2016-09-141-1/+0Star
| | | | | | | Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add event task of disable dynamic state managementEric Huang2016-07-071-0/+1
| | | | | | | | | Add an interface to disable dpm so that we can disable dpm before updating pptables at runtime. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Disable Spread Spectrum on DPM 0 on baffin as SPLL Shut ↵Rex Zhu2016-05-051-0/+1
| | | | | | | | Down feature is enabled. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: export interface to DAL.Rex Zhu2016-02-101-18/+24
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: change struct name.Rex Zhu2016-02-101-1/+1
| | | | | | | | amd_pp_dal_clock_info to amd_pp_simple_clock_info. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable power down asic task. (v2)Rex Zhu2016-01-081-0/+2
| | | | | | | | v2: AGD: rebase on upstream Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* amd/powerplay: Fix get dal power levelVitaly Prosyak2015-12-211-6/+1Star
| | | | | | Simplify data struct for get dal power level Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
* amd\powerplay Implement get dal power levelVitaly Prosyak2015-12-211-1/+27
| | | | | | Implement get dal power level and simple clock info Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
* drm/amd/powerplay: enable set_cpu_power_state task. (v2)Rex Zhu2015-12-211-0/+2
| | | | | | | | v2: integrate Jammy's crash fix Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
* drm/amd/powerplay: export interface to DAL to init/change display configuration.Rex Zhu2015-12-211-0/+3
| | | | | | | Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: David Rokhvarg <David.Rokhvarg@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
* drm/amd/powerplay: add and export hwmgr interface to eventmgr to check hw ↵Rex Zhu2015-12-211-0/+8
| | | | | | | | | | states. Interface between hwmgr and eventmgr. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
* drm/amdgpu/powerplay: add thermal control interface in hwmgr.Rex Zhu2015-12-211-0/+16
| | | | | | | | Thermal controller interface. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/poweprlay: export program display gap function to eventmgrRex Zhu2015-12-211-0/+2
| | | | | | | | | This allows the eventmgr to properly update the displaygap on certain power events. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add Tonga dpm support (v3)yanyang12015-12-211-9/+9
| | | | | | | | | | | | | | This implements DPM for tonga. DPM handles dynamic clock and voltage scaling. v2: merge all the patches related with tonga dpm v3: merge dpm force level fix, cgs display fix, spelling fix Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
* drm/amd/powerplay: add CG and PG support for carrizoRex Zhu2015-12-211-1/+52
| | | | | | | | | | This adds clock and powergating support for CZ. v2: squash in fixes Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: add hardware manager sub-componentJammy Zhou2015-12-211-0/+280
The hwmgr handles all hardware related calls, including clock/power gating control, DPM, read and parse PPTable, etc. v5: squash in fixes v4: implement acpi's atcs function use cgs interface v3: fix code style error and add big-endian mode support. v2: use cgs interface directly in hwmgr sub-module Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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