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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
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* Merge tag 'drm-intel-next-2018-07-09' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2018-07-181-24/+85
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| * drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva2018-07-051-0/+3
| * drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak2018-06-211-4/+35
| * drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHzImre Deak2018-06-211-20/+47
* | drm/i915: Use drm_plane_mask() & co.Ville Syrjälä2018-07-021-3/+3
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* drm/i915/icl: start adding the TBT pllPaulo Zanoni2018-06-141-4/+16
* drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare2018-06-021-0/+70
* drm/i915/icl: compute the MG PLL registersPaulo Zanoni2018-05-081-1/+222
* drm/i915/icl: compute the combo PHY (DPLL) DP registersPaulo Zanoni2018-05-081-1/+86
* drm/i915/icl: compute the combo PHY (DPLL) HDMI registersPaulo Zanoni2018-05-081-3/+36
* drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni2018-05-081-1/+312
* drm/i915: reorder dpll_info membersLucas De Marchi2018-03-271-24/+24
* drm/i915: use flags from dpll_info embedded in intel_shared_dpllLucas De Marchi2018-03-271-2/+0Star
* drm/i915: use id from intel_shared_dpll.infoLucas De Marchi2018-03-271-71/+89
* drm/i915: use name from intel_shared_dpll.infoLucas De Marchi2018-03-271-12/+14
* drm/i915: use funcs from intel_shared_dpll.infoLucas De Marchi2018-03-271-5/+4Star
* drm/i915: add dpll_info inside intel_shared_dpllLucas De Marchi2018-03-271-0/+1
* drm/i915: move dpll_info to headerLucas De Marchi2018-03-271-7/+0Star
* drm/i915/cnl: Simplify dco_fraction calculation.Rodrigo Vivi2017-11-161-3/+6
* drm/i915/cnl: Don't blindly replace qdiv.Rodrigo Vivi2017-11-161-2/+1Star
* drm/i915/cnl: Fix wrpll math for higher freqs.Rodrigo Vivi2017-11-161-3/+3
* drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.Rodrigo Vivi2017-11-161-18/+12Star
* drm/i915/cnl: Remove useless conversion.Rodrigo Vivi2017-11-161-3/+3
* drm/i915/cnl: Remove spurious central_freq.Rodrigo Vivi2017-11-161-1/+0Star
* drm/i915: Replace dig_port->port with encoder port for BXT DPLL selectionVille Syrjälä2017-11-091-9/+1Star
* drm/i915: Start using output_types for DPLL selectionVille Syrjälä2017-10-271-23/+13Star
* drm/i915: Adjust system agent voltage on CNL if required by DDI portsVille Syrjälä2017-10-251-8/+8
* drm/i915/cnl: Fix PLL initialization for HDMI.Rodrigo Vivi2017-10-171-1/+1
* drm/i915/cnl: Dump the right pll registers when dumping pipe config.Rodrigo Vivi2017-08-111-1/+10
* drm/i915/cnl: make function cnl_ddi_dp_set_dpll_hw_state staticColin Ian King2017-06-151-2/+3
* drm/i915/cnl: Enable wrpll computation for CNLKahola, Mika2017-06-121-2/+138
* drm/i915/cnl: Initialize PLLsRodrigo Vivi2017-06-121-2/+298
* drm/i915: Remove unused function intel_ddi_get_link_dpll()Ander Conselvan de Oliveira2017-02-101-44/+8Star
* drm/i915/bxt: Add MST support when do DPLL calculationLee, Shawn C2017-02-031-1/+2
* drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.Rodrigo Vivi2017-01-241-1/+1
* drm/i915: Move intel_atomic_get_shared_dpll_state() to intel_dpll_mgr.cAnder Conselvan de Oliveira2017-01-021-0/+31
* drm/i915: Add dpll entrypoint for dumping hw stateAnder Conselvan de Oliveira2016-12-301-0/+79
* drm/i915: Update kerneldoc for intel_dpll_mgr.cAnder Conselvan de Oliveira2016-12-301-5/+86
* drm/i915: Rename intel_shared_dpll->mode_set() to prepare()Ander Conselvan de Oliveira2016-12-301-4/+4
* drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_stateAnder Conselvan de Oliveira2016-12-301-36/+36
* drm/i915: Rename intel_shared_dpll_commit() to _swap_state()Ander Conselvan de Oliveira2016-12-301-1/+6
* drm/i915: Introduce intel_release_shared_dpll()Ander Conselvan de Oliveira2016-12-301-23/+18Star
* drm/i915/glk: Update Port PLL enable sequence for GeminilkaeMadhav Chauhan2016-12-021-0/+20
* drm/i915/glk: Set DCC delay range 2 in PLL enable sequenceAnder Conselvan de Oliveira2016-12-021-0/+6
* drm/i915/glk: Implement Geminilake DDI init sequenceAnder Conselvan de Oliveira2016-12-021-2/+2
* drm/i915/glk: Reuse broxton code for geminilakeAnder Conselvan de Oliveira2016-12-021-1/+1
* drm/i915: Assorted INTEL_INFO(dev) cleanupsTvrtko Ursulin2016-11-171-3/+2Star
* drm/i915: Address broxton phy registers based on phy and channel numberAnder Conselvan de Oliveira2016-10-281-38/+46
* drm/i915: Make IS_BROXTON only take dev_privTvrtko Ursulin2016-10-141-1/+1
* drm/i915: Make IS_KABYLAKE only take dev_privTvrtko Ursulin2016-10-141-1/+1
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