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* drm/nouveau/core: increase maximum number of nvdec instances to 3Ben Skeggs2018-12-111-3/+4
| | | | | | RTX2070 appears to have 3 copies of the engine. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/tu104: initial supportBen Skeggs2018-12-112-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/tu104: initial supportBen Skeggs2018-12-112-0/+2
| | | | | | Various different bits and pieces vs GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/tu104: initial supportBen Skeggs2018-12-112-0/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault/tu104: initial supportBen Skeggs2018-12-111-0/+1
| | | | | | | | | | | | New registers. Currently uncertain how exactly to mask fault buffer interrupts. This will likely be corrected at around the same time as the new MC interrupt stuff has been properly figured out and implemented. For the moment, it shouldn't matter too much. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bar/tu104: initial supportBen Skeggs2018-12-111-0/+1
| | | | | | New registers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mmu/tu104: initial supportBen Skeggs2018-12-111-0/+1
| | | | | | New flush method. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc/tu104: initial supportBen Skeggs2018-12-111-0/+1
| | | | | | | | | | Things are a bit different here on Turing, and will require further changes yet once I've investigated them more thoroughly. For now though, the existing GP100 code is compatible enough with one small hack to forward on fault buffer interrupts. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/devinit/tu104: initial supportBen Skeggs2018-12-111-0/+1
| | | | | | The GPU executes DEVINIT itself now, which makes our lives a bit easier. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: recognise TU104Ben Skeggs2018-12-112-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gv100: return work submission token in channel ctor argsBen Skeggs2018-12-112-1/+20
| | | | | | | The token will also contain runlist ID on Turing, so instead expose it as an opaque value from NVKM so the client doesn't need to care. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104-: support enabling privileged ce functionsBen Skeggs2018-12-111-1/+1
| | | | | | | Will be used by SVM code to allow direct (without going through MMU) memcpy using the GPU copy engines. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104-: return channel instance in ctor argsBen Skeggs2018-12-111-0/+1
| | | | | | Will be used to match fault buffer entries with a channel. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gf100-: call into BAR to reset BARs after MMU faultBen Skeggs2018-12-111-0/+2
| | | | | | | This is needed for Turing, but we're supposed to wait for completion after re-writing the value on older GPUs anyway. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/imem/nv50: support pinning objects in BAR2 and returning addressBen Skeggs2018-12-111-0/+2
| | | | | | | | | Various structures are accessed by the GPU through BAR2 for some reason on newer GPUs. This commit makes it more convenient to handle. Will be used for GP100- fault buffers, and GV100- fault method buffers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tmr: detect stalled gpu timer and break out of waitsBen Skeggs2018-12-111-10/+18
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios: translate USB-C connector typeBen Skeggs2018-12-111-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios: translate additional memory typesBen Skeggs2018-12-112-6/+12
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: support multiple nvdec instancesBen Skeggs2018-12-111-3/+6
| | | | | | Turing GPUs can have more than one. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp: add a way to configure scrambling/tmds for hdmi 2.0Ilia Mirkin2018-10-111-1/+4
| | | | | | | | | High pixel clocks are required to use a 40 TMDS divider instead of 10, and even low ones may optionally use scrambling depending on device support. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: remove const attribute from nvif_mclassNick Desaulniers2018-07-161-1/+1
| | | | | | | | | | | | Similar to commit 0bf8bf50eddc ("module: Remove const attribute from alias for MODULE_DEVICE_TABLE") Fixes many -Wduplicate-decl-specifier warnings due to the combination of const typeof() of already const variables. Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gv100: initial supportBen Skeggs2018-05-182-0/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce/gv100: initial supportBen Skeggs2018-05-182-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gv100: initial supportBen Skeggs2018-05-184-0/+26
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/gv100: initial supportBen Skeggs2018-05-184-0/+32
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dma/gv100: initial supportBen Skeggs2018-05-181-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault/gv100: initial supportBen Skeggs2018-05-181-1/+5
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mmu/gv100: initial supportBen Skeggs2018-05-181-0/+1
| | | | | | | | VEID support hacked in here, as it's the most convenient place for now. Will be refined once it's better understood. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/gv100: initial supportBen Skeggs2018-05-181-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/devinit/gv100: initial supportBen Skeggs2018-05-181-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: recognise gv100Ben Skeggs2018-05-182-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: increase maximum number of copy engines to 9Ben Skeggs2018-05-181-3/+6
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/kms/nv50-: determine MST support from DP Info TableBen Skeggs2018-05-181-0/+4
| | | | | | | GV100 doesn't support MST, use the information provided in VBIOS tables to detect its presence instead. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/kms: move display class instantiation to libraryBen Skeggs2018-05-182-0/+28
| | | | | | This function is useful outside of DRM code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gp102-: setup stencil zbcBen Skeggs2018-05-181-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gf100-: update r408840 where requiredBen Skeggs2018-05-181-0/+1
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104-: require explicit runlist selection for channel ↵Ben Skeggs2018-05-181-16/+2Star
| | | | | | | | | | | | | | | | | allocation We didn't used to be aware that runlist/engine IDs weren't the same thing, or that there was such variability in configuration between GPUs. By exposing this information to a client, and giving it explicit control of which runlist it's allocating a channel on, we're able to make better choices. The immediate effect of this is that on GPUs where CE0 is the "GRCE", we will now be allocating a copy engine running asynchronously to GR for BO migrations - as intended. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104-: support querying engines available on each runlistBen Skeggs2018-05-183-0/+30
| | | | | | Will be used to improve channel runlist selection. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104-: allow fault recovery code to be called by other subdevsBen Skeggs2018-05-182-0/+15
| | | | | | This will be required to support Volta. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: support channel count queryBen Skeggs2018-05-182-1/+4
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/device: support querying available engines of a specific typeBen Skeggs2018-05-181-0/+19
| | | | | | Will be used for fifo runlist selection. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/device: implement a generic method to query device-specific ↵Ben Skeggs2018-05-183-0/+19
| | | | | | | | | | | properties We have a need to fetch data from GPU-specific sub-devices that is not tied to any particular engine object. This commit provides the framework to support such queries. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp/nv50-: pass nvkm_memory objects for channel push buffersBen Skeggs2018-05-182-0/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault/gp100: implement replayable fault buffer initialisationBen Skeggs2018-05-181-0/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fault: add infrastructure to support fault buffersBen Skeggs2018-05-181-0/+6
| | | | | | GPU-specific support will be added separately. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: define FAULT subdevBen Skeggs2018-05-182-0/+11
| | | | | | | This will be responsible for the handling of MMU fault buffers on GPUs that support them. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* Merge tag 'drm-for-v4.16-part2-fixes' of ↵Linus Torvalds2018-02-083-0/+19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~airlied/linux Pull more drm updates from Dave Airlie: "Ben missed sending his nouveau tree, but he really didn't have much stuff in it: - GP108 acceleration support is enabled by "secure boot" support - some clockgating work on Kepler, and bunch of fixes - the bulk of the diff is regenerated firmware files, the change to them really isn't that large. Otherwise this contains regular Intel and AMDGPU fixes" * tag 'drm-for-v4.16-part2-fixes' of git://people.freedesktop.org/~airlied/linux: (59 commits) drm/i915/bios: add DP max link rate to VBT child device struct drm/i915/cnp: Properly handle VBT ddc pin out of bounds. drm/i915/cnp: Ignore VBT request for know invalid DDC pin. drm/i915/cmdparser: Do not check past the cmd length. drm/i915/cmdparser: Check reg_table_count before derefencing. drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changing drm/i915/gvt: Use KVM r/w to access guest opregion drm/i915/gvt: Fix aperture read/write emulation when enable x-no-mmap=on drm/i915/gvt: only reset execlist state of one engine during VM engine reset drm/i915/gvt: refine intel_vgpu_submission_ops as per engine ops drm/amdgpu: re-enable CGCG on CZ and disable on ST drm/nouveau/clk: fix gcc-7 -Wint-in-bool-context warning drm/nouveau/mmu: Fix trailing semicolon drm/nouveau: Introduce NvPmEnableGating option drm/nouveau: Add support for SLCG for Kepler2 drm/nouveau: Add support for BLCG on Kepler2 drm/nouveau: Add support for BLCG on Kepler1 drm/nouveau: Add support for basic clockgating on Kepler1 drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion drm/nouveau/kms/nv50: use INTERPOLATE_257_UNITY_RANGE LUT on newer chipsets ...
| * drm/nouveau: Add support for BLCG on Kepler2Lyude Paul2018-02-021-0/+1
| | | | | | | | | | | | | | | | Same as the previous patch, but for Kepler2 now Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau: Add support for BLCG on Kepler1Lyude Paul2018-02-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables BLCG optimization for kepler1. When using clockgating, nvidia's firmware has a set of registers which are initially programmed by the vbios with various engine delays and other mysterious settings that are safe enough to bring up the GPU. However, the values used by the vbios are more power hungry then they need to be, so the nvidia driver writes it's own more optimized set of BLCG settings before enabling CG_CTRL. This adds support for programming the optimized BLCG values during engine/subdev init, which enables rather significant power savings. This introduces the nvkm_therm_clkgate_init() helper, which we use to program the optimized BLCG settings before enabling clockgating with nvkm_therm_clkgate_enable. As well, this commit shares a lot more code with Fermi since BLCG is mostly the same there as far as we can tell. In the future, it's likely we'll reformat the clkgate_packs for kepler1 so that they share a list of mmio packs with Fermi. Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| * drm/nouveau: Add support for basic clockgating on Kepler1Lyude Paul2018-02-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for enabling automatic clockgating on nvidia GPUs for Kepler1. While this is not technically a clockgating level, it does enable clockgating using the clockgating values initially set by the vbios (which should be safe to use). This introduces two therm helpers for controlling basic clockgating: nvkm_therm_clkgate_enable() - enables clockgating through CG_CTRL, done after initializing the GPU fully nvkm_therm_clkgate_fini() - prepares clockgating for suspend or driver unload A lot of this code was originally going to be based off of fermi; however it turns out that while Fermi's the first line of GPUs that introduced this kind of power saving, Fermi requires more fine tuned control of the CG_CTRL registers from the driver while reclocking that we don't entirely understand yet. For the simple parts we will be sharing with Fermi for certain however, we at least add those into a new subdev/therm/gf100.h header. Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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