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path: root/drivers/gpu/drm
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* drm/amdkfd: Fix incorrect use of process->mmFelix Kuehling2018-10-101-8/+29
| | | | | | | | | | | This mm_struct pointer should never be dereferenced. If running in a user thread, just use current->mm. If running in a kernel worker use get_task_mm to get a safe reference to the mm_struct. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: skip IB tests for KIQ in generalPratik Vishwakarma2018-10-101-0/+8
| | | | | | | | | | | | | | | | [Why] 1. We never submit IBs to KIQ. 2. Ring test pass without KIQ's ring also. 3. By skipping we see an improvement of around 500ms in the amdgpu's resume time. [How] skip IB tests for KIQ ring type. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/scheduler: Simplify spsc_queue_count check in drm_sched_entity_select_rqNathan Chancellor2018-10-101-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang generates a warning when it sees a logical not followed by a conditional operator like ==, >, or <. drivers/gpu/drm/scheduler/sched_entity.c:470:6: warning: logical not is only applied to the left hand side of this comparison [-Wlogical-not-parentheses] if (!spsc_queue_count(&entity->job_queue) == 0 || ^ ~~ drivers/gpu/drm/scheduler/sched_entity.c:470:6: note: add parentheses after the '!' to evaluate the comparison first if (!spsc_queue_count(&entity->job_queue) == 0 || ^ ( ) drivers/gpu/drm/scheduler/sched_entity.c:470:6: note: add parentheses around left hand side expression to silence this warning if (!spsc_queue_count(&entity->job_queue) == 0 || ^ ( ) 1 warning generated. It assumes the author might have made a mistake in their logic: if (!a == b) -> if (!(a == b)) Sometimes that is the case; other times, it's just a super convoluted way of saying 'if (a)' when b = 0: if (!1 == 0) -> if (0 == 0) -> if (true) Alternatively: if (!1 == 0) -> if (!!1) -> if (1) Simplify this comparison so that Clang doesn't complain. Fixes: 35e160e781a0 ("drm/scheduler: change entities rq even earlier") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Refine smu7/8 request_smu_load_fw callback functionRex Zhu2018-10-103-73/+39Star
| | | | | | | | | | | | | | | | | The request_smu_load_fw of VI is used to load gfx/sdma ip's firmware. Check whether the gfx/sdma firmware have been loaded successfully in this callback function. if failed, driver can exit to avoid gpu hard hung. if successful, clean the flag reload_fw to avoid duplicated fw load. when suspend/resume, driver need to reload fw. so in suspend, reset the reload_fw flag to true to enable load fw when resume. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Setup SoftRegsStart before request smu load fwRex Zhu2018-10-102-1/+19
| | | | | | | | | need to know SoftRegsStart value to visit the register UcodeLoadStatus to check fw loading state. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Refine function iceland_start_smuRex Zhu2018-10-101-11/+1Star
| | | | | | | | | | if upload firmware failed, no matter how many times the function runs again, the same error will be encountered. so remove the duplicated code. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Move gfx flag in_suspend to adevRex Zhu2018-10-105-24/+14Star
| | | | | | | | | | Move in_suspend flag to adev from gfx, so can be used in other ip blocks, also keep consistent with gpu_in_reset flag. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Fix memory leak on CI/AIRex Zhu2018-10-101-4/+4
| | | | | | | | | | On CI/AI, fw was not loaded by smu, but smu's fw still need to be released when driver fini. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Drop dead define in amdgpu.hRex Zhu2018-10-101-28/+0Star
| | | | | | | | the struct was not in use any more. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Always enable fan sensors for readRex Zhu2018-10-101-10/+0Star
| | | | | | | | don't need to set fan1_enable to read fan sensors. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Disable sysfs pwm1 if not in manual fan controlRex Zhu2018-10-101-0/+7
| | | | | | | | | | Following lm-sensors 3.0.0, Only enable pwm1 sysfs when fan control mode(pwm1_enable) in manual Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add fan RPM setting via sysfsRex Zhu2018-10-104-3/+210
| | | | | | | | | | | | | | Add fan1_target for get/set fan speed in RPM unit Add fan1_min/fan1_max for get min, max fan speed in RPM unit Add fan1_enable to enable/disable the fan1 sensor v3: drop the hardcode value of min/max rpm in comments pointed out by Alex. v2: query the min/max rpm gpu support instand of hardcode value. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Implement AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPMRex Zhu2018-10-102-0/+8
| | | | | | | | so user can query the RPM range Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Add new AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM sensorRex Zhu2018-10-101-0/+2
| | | | | | | | For getting the min/max fan speed in RPM units. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msgRex Zhu2018-10-102-15/+7Star
| | | | | | | | | 1. make uvd_v7_0_enc_get_destroy_msg static 2. drop a function variable that always true Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Signal hw_done() after waiting for flip_done()Shirish S2018-10-101-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In amdgpu_dm_commit_tail(), wait until flip_done() is signaled before we signal hw_done(). [Why] This is to temporarily address a paging error that occurs when a nonblocking commit contends with another commit, particularly in a mirrored display configuration where at least 2 CRTCs are updated. The error occurs in drm_atomic_helper_wait_for_flip_done(), when we attempt to access the contents of new_crtc_state->commit. Here's the sequence for a mirrored 2 display setup (irrelevant steps left out for clarity): **THREAD 1** | **THREAD 2** | Initialize atomic state for flip | | Queue worker | ... | Do work for flip | | Signal hw_done() on CRTC 1 | Signal hw_done() on CRTC 2 | | Wait for flip_done() on CRTC 1 <---- **PREEMPTED BY THREAD 1** Initialize atomic state for cursor | update (1) | | Do cursor update work on both CRTCs | | Clear atomic state (2) | **DONE** | ... | | Wait for flip_done() on CRTC 2 | *ERROR* | The issue starts with (1). When the atomic state is initialized, the current CRTC states are duplicated to be the new_crtc_states, and referenced to be the old_crtc_states. (The new_crtc_states are to be filled with update data.) Some things to note: * Due to the mirrored configuration, the cursor updates on both CRTCs. * At this point, the pflip IRQ has already been handled, and flip_done signaled on all CRTCs. The cursor commit can therefore continue. * The old_crtc_states used by the cursor update are the **same states** as the new_crtc_states used by the flip worker. At (2), the old_crtc_state is freed (*), and the cursor commit completes. We then context switch back to the flip worker, where we attempt to access the new_crtc_state->commit object. This is problematic, as this state has already been freed. (*) Technically, 'state->crtcs[i].state' is freed, which was made to reference old_crtc_state in drm_atomic_helper_swap_state() [How] By moving hw_done() after wait_for_flip_done(), we're guaranteed that the new_crtc_state (from the flip worker's perspective) still exists. This is because any other commit will be blocked, waiting for the hw_done() signal. Note that both the i915 and imx drivers have this sequence flipped already, masking this problem. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Use proper enums in process_channel_replyNathan Chancellor2018-10-102-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Clang warns when one enumerated type is implicitly converted to another. drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:315:19: warning: implicit conversion from enumeration type 'enum aux_channel_operation_result' to different enumeration type 'enum aux_transaction_reply' [-Wenum-conversion] reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/i2caux/dce110/aux_engine_dce110.c:349:19: warning: implicit conversion from enumeration type 'enum aux_channel_operation_result' to different enumeration type 'enum aux_transaction_reply' [-Wenum-conversion] reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON; ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The current enum is incorrect, it should be from aux_transaction_reply, so use AUX_TRANSACTION_REPLY_HPD_DISCON. Reported-by: Nick Desaulniers <ndesaulniers@google.com> Suggested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Raise dispclk value for dce_update_clocksNicholas Kazlauskas2018-10-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | [Why] The DISPCLK value was previously requested to be 15% higher for all ASICS that went through the dce110 bandwidth code path. As part of a refactoring of dce_clocks and dce110 set_bandwidth this was removed for power saving considerations. This changed caused corruption under certain display configurations. Originally thought to be Vega specific, it was also observed on Polaris. [How] The 15% is brought back but its placement differs from the original patch. This boost should only be enable while DFS bypass is inactive. This (like the Vega patch) is also a workaround that should be removed after the root cause is identified. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: HLK Periodic Frame Notification test failedMurton Liu2018-10-101-1/+1
| | | | | | | | | | | | | | [Why] Due to a small pre-fetch window, the active vline timing is a couple of lines off when compared to what it should be. [How] Changed the calculation for the start vline to account for this window. Signed-off-by: Murton Liu <murton.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix Interlace video timing.Charlene Liu2018-10-101-25/+7Star
| | | | | | | | | | | | [Description] interlace mode shows wrong vertical timing. Interface timing in Edid is half vertical timing as progressive timing. driver doubled the vertical timing in edid_paser, no need to double in optc again. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Flatten irq handler data structLeo Li2018-10-101-23/+14Star
| | | | | | | | | | | | | [Why] There is no reason why the common data needs to be kept separate. [How] Flatten the struct by moving common data into the DM IRQ struct. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix memory leak in resource poolsJun Lei2018-10-106-3/+15
| | | | | | | | | | | | | | | | | [why] ddc engines were recently changed to be independently tracked from pipe count. the change was reflected in resource constructor but not in destructor. this manifests as a memory leak when pipe harvesting is enabled, since not all constructed ddc engines are freed [how] make destructor symmetric with constructor for all dcX_resource Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: dc 3.1.68Tony Cheng2018-10-101-1/+1
| | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: WA for DF keeps awake after S0i3.Yongqiang Sun2018-10-103-0/+35
| | | | | | | | | | | | | | | | [Why] DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL is set by bios command table during dcn init_hw. [How] As a work around, check STATE_CNTL status before init_hw, if it is 0 before init_hw and set to 1 after init_hw, change it to 0. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: clean up encoding checksEric Yang2018-10-109-43/+7Star
| | | | | | | | | | | | | [Why] All ASICS we support has YCbCr support, so the check is unnecessary, the currently logic in validate output also returns true all the time, so the unneccessary logic is removed Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: block DP YCbCr420 modesEric Yang2018-10-102-0/+6
| | | | | | | | | | | | | [why] Currently not supported, will black screen when set. [How] Fail validate timing helper for those modes. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add function to fetch clock requirementsEryk Brol2018-10-103-1/+28
| | | | | | | | | Also add dram clock to clocks struct, for systems that uses them. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Calculate swizzle mode using bpp during validationSu Sung Chung2018-10-106-30/+67
| | | | | | | | | | | | | | | | | | | | [Why] Previously bandwidth validation was failing because swizzle mode was not initialized during plane_state allocation. The swizzle mode was calculated using pixed format which is how swizzle mode is initially calculated in addrlib. [How] * Set default swizzle mode for validation to DC_SW_UNKNOWN * Created new function in dcn10_assign_swizzle_mode which sets the plane swizzle mode based on selected pixed format * Added the call of assign_swizzle_mode into dc_validate_global_state * Set failsafe swizzle mode back to DC_SW_LINEAR Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add a check-function for virtual signal typeNikola Cornij2018-10-101-0/+5
| | | | | | | | | | | | [why] Same functions exist for all other signal types. [how] Add a function that checks against virtual signal type. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: fix 4K stereo screen flash issueCharlene Liu2018-10-101-0/+3
| | | | | | | | | | | | [Why] HDMI_scramber is not enabled for pixel rate >340Mhz. [How] Calculate the phy clock to include the Hw frame packing factor. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/display: Add DC build_id to determine build typeJun Lei2018-10-102-0/+5
| | | | | | | | | | | | | | | | | [why] Sometimes there are indications that the incorrect driver is being loaded in automated tests. This change adds the ability for builds to be tagged with a string, and picked up by the test infrastructure. [how] dc.c will allocate const for build id, which is init-ed with default value, indicating production build. For test builds, build server will find/replace this value. The test machine will then verify this value. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVDAkshu Agrawal2018-10-101-1/+4
| | | | | | | | | | | | | We observe black lines (underflow) on display when playing a 4K video with UVD. On Disabling Low memory P state this issue is not seen. Multiple runs of power measurement shows no imapct. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/amd/pp: Remove wrong code in fiji_start_smuRex Zhu2018-10-101-10/+0Star
| | | | | | | | HW CG feature will be enabled after hw ip initialized Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Remove uncessary extra vcn pg cntl in smuRex Zhu2018-10-101-15/+1Star
| | | | | | | | the vcn power will be controlled by VCN. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Move out power up/down sdma out of smuRex Zhu2018-10-103-15/+7Star
| | | | | | | | | smu only expose interface to other ip blocks. in order to reduce dependence between smu and other ip blocks Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Expose the smu support for SDMA PG cntlRex Zhu2018-10-103-0/+27
| | | | | | | | SDMA IP can be power up/down via smu message Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpmRex Zhu2018-10-102-0/+2
| | | | | | | | | The minRPM speed maybe equal to zero. so need to check input RPM not equal to 0, otherwise cause divide-by-zero driver crash. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10Rex Zhu2018-10-102-4/+4
| | | | | | | | set the target rpm value to wrong register. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gatingRex Zhu2018-10-101-1/+1
| | | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: enable MGPU fan boost feature on Vega20Evan Quan2018-10-101-0/+15
| | | | | | | | | Added Vega20 specific implementation for MGPU fan boost feature. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay: helper interfaces for MGPU fan boost featureEvan Quan2018-10-095-0/+66
| | | | | | | | | MGPU fan boost feature is enabled only when two or more dGPUs in the system. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: added AMD GPU instance counting V2Evan Quan2018-10-093-0/+73
| | | | | | | | | | | | Count all GPU instances from AMD(including iGPUs and dGPUs) in the system. V2: drop unnecessary initialization for other gpu_info members except mutex Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu/vega20: make power profile output more consistentAlex Deucher2018-10-091-1/+1
| | | | | | | | | | | | Make the profile name line match previous generations more closely. E.g., 0 3D_FULL_SCREEN : vs: 0(3D_FULL_SCREEN ) Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: change Raven always on CUs to 4Evan Quan2018-10-091-2/+6
| | | | | | | | | For Vega10 and Vega20, the always on CUs are 12. For Raven, it's 4. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: added vega20 LBPW support v2Evan Quan2018-10-091-1/+104
| | | | | | | | | | Enable LBPW support on vega20. v2: squash in warning fix (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2Evan Quan2018-10-095-4/+207
| | | | | | | | | | | | | Manual fan RPM and pwm setting on vega20 are available now. V2: correct the register for fan speed setting and avoid divide-by-zero Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay/vega20: tell the correct gfx voltage V2Evan Quan2018-10-093-0/+18
| | | | | | | | | | Export the correct gfx voltage by hwmon interface. V2: update the register naming for consistency Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amd/powerplay/vega20: correct the hwmon interface ppt limit outputEvan Quan2018-10-092-0/+14
| | | | | | | | | | The ppt limit read out by hwmon interface is always 0. Correct this hwmon interface output. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into ↵Dave Airlie2018-10-047-73/+520
|\ | | | | | | | | | | | | | | | | | | drm-next misc mali-dp updates. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Liviu Dudau <Liviu.Dudau@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181003105009.GD1156@e110455-lin.cambridge.arm.com
| * drm/arm/malidp: Implemented the size validation for AFBC framebuffersAyan Kumar Halder2018-10-022-1/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AFBC buffers include additional metadata which increases the required allocation size. Implement the appropriate size validation and sanity checking for AFBC buffers. Added malidp specific function for framebuffer creation. This checks if the framebuffer has AFBC modifiers and if so, it verifies the necessary constraints on the size, alignment, offsets and pitch. Changes from v2: - Replaced DRM_ERROR() with DRM_DEBUG_KMS() in malidp_verify_afbc_framebuffer_caps() and malidp_verify_afbc_framebuffer_size() Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
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