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* coresight: tpiu: retrieve and handle atclkLinus Walleij2015-05-241-0/+37
| | | | | | | | | | | | | | | | | | | | | | As can be seen from the datasheet of the CoreSight Components, DDI0314H page A-19 the TPIU has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks in conjunction. The ATCLK is enabled and disabled using the runtime PM callbacks. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etm: retrieve and handle atclkLinus Walleij2015-05-242-1/+37
| | | | | | | | | | | | | | | | | | | | | | As can be seen from the datasheet of the CoreSight Components, DDI0401C A.1.1 the ETM has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks. The ATCLK is enabled and disabled using the runtime PM callbacks. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: tmc: let runtime PM handle core clockLinus Walleij2015-05-241-23/+8Star
| | | | | | | | | | | | | | | | | | | | | This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: funnel: let runtime PM handle core clockLinus Walleij2015-05-241-17/+7Star
| | | | | | | | | | | | | | | | | | | This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as clk_disable_unprepare() was not called. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etb: let runtime PM handle core clockLinus Walleij2015-05-241-26/+9Star
| | | | | | | | | | | | | | | | | | | | | This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: tpiu: let runtime PM handle core clockLinus Walleij2015-05-241-17/+4Star
| | | | | | | | | | | | | | | | | | | | | This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etm: let runtime PM handle core clockLinus Walleij2015-05-242-46/+16Star
| | | | | | | | | | | | | | | | | | | | | This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: support the TPIU version found in Ux500Linus Walleij2015-05-241-0/+4
| | | | | | | | | | The Ux500 has a PrimeCell version 4B instead of the 3B as supported by the driver, extend the match table to cover this version. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etm: print what version of ETM/PTM is detectedLinus Walleij2015-05-241-1/+5
| | | | | | | | | | Helpfully report a bit more about the hardware found in the silicon when matching the AMBA device IDs by using the associated .data pointer in the AMBA match. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm3x: use module_amba_driver to simplify the codeMathieu Poirier2015-05-241-11/+1Star
| | | | | | | | | | | Using function "module_amba_driver()" makes the code simpler by eliminating boilerplate code. Wei Yongjun sent out a set of patches addressing those in all the coresight driver but missed ETMv3. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Read only access to the tracer's ID registersMathieu Poirier2015-05-241-0/+37
| | | | | | | | | ETM ID registers contain valuable information about the capabilities of the implementation and are very useful when configuring the device for various trace scenarios. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Read only access to the main management registersMathieu Poirier2015-05-241-1/+52
| | | | | | | | | Having access to the ETMv4 management registers is very useful as they give meaningful information on how the IP block has been configured at synthesis time. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the VM ID functionsPratik Patel2015-05-241-0/+178
| | | | | | | | | Adding sysfs entries to access and configure specifics about the virtual machine ID comparator functions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the context ID functionsPratik Patel2015-05-241-0/+187
| | | | | | | | | Adding sysfs entries to access and configure specifics about the context ID comparator functions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the selection of resourcesPratik Patel2015-05-241-0/+75
| | | | | | | | | Adding sysfs entries to control the selection of the resources the trace unit will use as triggers to perform a trace run. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the counter functionsPratik Patel2015-05-241-0/+144
| | | | | | | | | Adding sysfs entries related to the counter functionality, more specifically to set, control and reload the counters. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the sequencer functionsPratik Patel2015-05-241-0/+129
| | | | | | | | | | Adding sysfs entries to access the sequencers related registers, more specifically the sequencer state, the sequencer state transition and the sequencer reset control registers. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the address comparator functionsPratik Patel2015-05-241-0/+423
| | | | | | | | | | | Adding sysfs entries to control the various mode the address comparator registers can enact, i.e, start/top, single, and range. Also supplementing with address comparator types configuration registers access, mandatory to complete the configuration of the comparator functions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the ViewInst registerPratik Patel2015-05-241-0/+98
| | | | | | | | | | Adding sysfs entries to control the ViewInst register's event selector along with secure and non-secure exception level instruction tracing. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to various configuration optionsPratik Patel2015-05-241-0/+124
| | | | | | | | | | | | Adding sysfs entries to configure: . global timestamp. . how often trace synchronisation occur. . the threashold value for cycle counting. . branch and broadcasting regions. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to the reset, mode, pe and eventsPratik Patel2015-05-241-0/+441
| | | | | | | | | | | | Adding sysfs entries to: . set the tracing entity with default values. . set various mode associated to the tracing entity. . select the processing entity the tracing entity relates to. . select various events of interest. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Controls pertaining to tracer configurationPratik Patel2015-05-241-0/+117
| | | | | | | | | | | | | Tracers can be configured with various options at synthesis time and knowing what resources are available is important for SW configuration purposes. As such adding RO sysfs entries for characteristics related to the tracer implementation. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight-etm4x: Adding CoreSight ETM4x driverPratik Patel2015-05-244-0/+1100
| | | | | | | | | | This driver manages the CoreSight ETMv4 (Embedded Trace Macrocell) IP block to support HW assisted tracing on ARMv7 and ARMv8 architectures. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Kaixu Xia <xiakaixu@huawei.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etb10: Fix check for bogus buffer depthMark Brown2015-05-181-1/+1
| | | | | | | | | | | We attempt to sanity check the buffer depth reported by the hardware by making sure it is not less than zero however this check will never be true since the buffer depth is stored in an unsigned integer. Instead change the check to look for the top bit being set which was the intention. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* coresight: etb10: Print size of buffer we fail to allocateMark Brown2015-05-181-1/+4
| | | | | | | | | | | | | | | | | | | When we initialise the ETB driver we attempt to allocate a buffer suitable for storing the data buffered in the hardware based on sizing information reported by the hardware. Unfortunately if the hardware is not properly configured (for example if power domains are not set up correctly) then we may read back a nonsensically large value and therefore the allocation will be too big to succeed. Print an error message showing the amount of memory we tried to allocate if the buffer allocation fails to help users diagnose such problems. Normally it is bad practice to print an error message on memory allocation failures since there are verbose core messages reported for this but in this case where the allocation size might be incorrect it is a useful hint. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'char-misc-4.1-rc1' of ↵Linus Torvalds2015-04-211-11/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here's the big char/misc driver patchset for 4.1-rc1. Lots of different driver subsystem updates here, nothing major, full details are in the shortlog. All of this has been in linux-next for a while" * tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (133 commits) mei: trace: remove unused TRACE_SYSTEM_STRING DTS: ARM: OMAP3-N900: Add lis3lv02d support Documentation: DT: lis302: update wakeup binding lis3lv02d: DT: add wakeup unit 2 and wakeup threshold lis3lv02d: DT: use s32 to support negative values Drivers: hv: hv_balloon: correctly handle num_pages>INT_MAX case Drivers: hv: hv_balloon: correctly handle val.freeram<num_pages case mei: replace check for connection instead of transitioning mei: use mei_cl_is_connected consistently mei: fix mei_poll operation hv_vmbus: Add gradually increased delay for retries in vmbus_post_msg() Drivers: hv: hv_balloon: survive ballooning request with num_pages=0 Drivers: hv: hv_balloon: eliminate jumps in piecewiese linear floor function Drivers: hv: hv_balloon: do not online pages in offline blocks hv: remove the per-channel workqueue hv: don't schedule new works in vmbus_onoffer()/vmbus_onoffer_rescind() hv: run non-blocking message handlers in the dispatch tasklet coresight: moving to new "hwtracing" directory coresight-tmc: Adding a status interface to sysfs coresight: remove the unnecessary configuration coresight-default-sink ...
* coresight: moving to new "hwtracing" directoryMathieu Poirier2015-04-0313-0/+5780
Keeping drivers related to HW tracing on ARM, i.e coresight, under "drivers/coresight" doesn't make sense when other architectures start rolling out technologies of the same nature. As such creating a new "drivers/hwtracing" directory where all drivers of the same kind can reside, reducing namespace pollution under "drivers/". Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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