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* | mmc: sdhci-xenon: kill xenon_clean_phy()Jisheng Zhang2017-05-193-19/+2Star
|/ | | | | | | | | | Currently, the xenon_clean_phy() is only used for freeing phy_params. The phy_params is allocated by devm_kzalloc(), there's no need to free is explicitly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Hu Ziji <huziji@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
* Merge tag 'hwparam-20170420' of ↵Linus Torvalds2017-05-111-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs Pull hw lockdown support from David Howells: "Annotation of module parameters that configure hardware resources including ioports, iomem addresses, irq lines and dma channels. This allows a future patch to prohibit the use of such module parameters to prevent that hardware from being abused to gain access to the running kernel image as part of locking the kernel down under UEFI secure boot conditions. Annotations are made by changing: module_param(n, t, p) module_param_named(n, v, t, p) module_param_array(n, t, m, p) to: module_param_hw(n, t, hwtype, p) module_param_hw_named(n, v, t, hwtype, p) module_param_hw_array(n, t, hwtype, m, p) where the module parameter refers to a hardware setting hwtype specifies the type of the resource being configured. This can be one of: ioport Module parameter configures an I/O port iomem Module parameter configures an I/O mem address ioport_or_iomem Module parameter could be either (runtime set) irq Module parameter configures an I/O port dma Module parameter configures a DMA channel dma_addr Module parameter configures a DMA buffer address other Module parameter configures some other value Note that the hwtype is compile checked, but not currently stored (the lockdown code probably won't require it). It is, however, there for future use. A bonus is that the hwtype can also be used for grepping. The intention is for the kernel to ignore or reject attempts to set annotated module parameters if lockdown is enabled. This applies to options passed on the boot command line, passed to insmod/modprobe or direct twiddling in /sys/module/ parameter files. The module initialisation then needs to handle the parameter not being set, by (1) giving an error, (2) probing for a value or (3) using a reasonable default. What I can't do is just reject a module out of hand because it may take a hardware setting in the module parameters. Some important modules, some ipmi stuff for instance, both probe for hardware and allow hardware to be manually specified; if the driver is aborts with any error, you don't get any ipmi hardware. Further, trying to do this entirely in the module initialisation code doesn't protect against sysfs twiddling. [!] Note that in and of itself, this series of patches should have no effect on the the size of the kernel or code execution - that is left to a patch in the next series to effect. It does mark annotated kernel parameters with a KERNEL_PARAM_FL_HWPARAM flag in an already existing field" * tag 'hwparam-20170420' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs: (38 commits) Annotate hardware config module parameters in sound/pci/ Annotate hardware config module parameters in sound/oss/ Annotate hardware config module parameters in sound/isa/ Annotate hardware config module parameters in sound/drivers/ Annotate hardware config module parameters in fs/pstore/ Annotate hardware config module parameters in drivers/watchdog/ Annotate hardware config module parameters in drivers/video/ Annotate hardware config module parameters in drivers/tty/ Annotate hardware config module parameters in drivers/staging/vme/ Annotate hardware config module parameters in drivers/staging/speakup/ Annotate hardware config module parameters in drivers/staging/media/ Annotate hardware config module parameters in drivers/scsi/ Annotate hardware config module parameters in drivers/pcmcia/ Annotate hardware config module parameters in drivers/pci/hotplug/ Annotate hardware config module parameters in drivers/parport/ Annotate hardware config module parameters in drivers/net/wireless/ Annotate hardware config module parameters in drivers/net/wan/ Annotate hardware config module parameters in drivers/net/irda/ Annotate hardware config module parameters in drivers/net/hamradio/ Annotate hardware config module parameters in drivers/net/ethernet/ ...
| * Annotate hardware config module parameters in drivers/mmc/host/David Howells2017-04-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the kernel is running in secure boot mode, we lock down the kernel to prevent userspace from modifying the running kernel image. Whilst this includes prohibiting access to things like /dev/mem, it must also prevent access by means of configuring driver modules in such a way as to cause a device to access or modify the kernel image. To this end, annotate module_param* statements that refer to hardware configuration and indicate for future reference what type of parameter they specify. The parameter parser in the core sees this information and can skip such parameters with an error message if the kernel is locked down. The module initialisation then runs as normal, but just sees whatever the default values for those parameters is. Note that we do still need to do the module initialisation because some drivers have viable defaults set in case parameters aren't specified and some drivers support automatic configuration (e.g. PNP or PCI) in addition to manually coded parameters. This patch annotates drivers in drivers/mmc/host/. Suggested-by: Alan Cox <gnomes@lxorguk.ukuu.org.uk> Signed-off-by: David Howells <dhowells@redhat.com> cc: Pierre Ossman <pierre@ossman.eu> cc: Ulf Hansson <ulf.hansson@linaro.org> cc: linux-mmc@vger.kernel.org
* | Merge tag 'mmc-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmcLinus Torvalds2017-05-0364-1612/+7522
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MMC updates from Ulf Hansson: "MMC core: - Continue to re-factor code to prepare for eMMC CMDQ and blkmq support - Introduce queue semantics to prepare for eMMC CMDQ and blkmq support - Add helper functions to manage temporary enable/disable of eMMC CMDQ - Improve wait-busy detection for SDIO MMC host: - cavium: Add driver to support Cavium controllers - cavium: Extend Cavium driver to support Octeon and ThunderX SOCs - bcm2835: Add new driver for Broadcom BCM2835 controller - sdhci-xenon: Add driver to support Marvell Xenon SDHCI controller - sdhci-tegra: Add support for the Tegra186 variant - sdhci-of-esdhc: Support for UHS-I SD cards - sdhci-of-esdhc: Support for eMMC HS200 cards - sdhci-cadence: Add eMMC HS400 enhanced strobe support - sdhci-esdhc-imx: Reset tuning circuit when needed - sdhci-pci: Modernize and clean-up some PM related code - sdhci-pci: Avoid re-tuning at runtime PM for some Intel devices - sdhci-pci|acpi: Use aggressive PM for some Intel BYT controllers - sdhci: Re-factoring and modernizations - sdhci: Optimize delay loops - sdhci: Improve register dump print format - sdhci: Add support for the Command Queue Engine - meson-gx: Various improvements and clean-ups - meson-gx: Add support for CMD23 - meson-gx: Basic tuning support to avoid CRC errors - s3cmci: Enable probing via DT - mediatek: Improve tuning support for eMMC HS200 and HS400 mode - tmio: Improve DMA support - tmio: Use correct response for CMD12 - dw_mmc: Minor improvements and clean-ups" * tag 'mmc-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (148 commits) mmc: sdhci-of-esdhc: limit SD clock for ls1012a/ls1046a mmc: sdhci-of-esdhc: poll ESDHC_CLOCK_STABLE bit with udelay mmc: sdhci-xenon: Fix default value of LOGIC_TIMING_ADJUST for eMMC5.0 PHY mmc: sdhci-xenon: Fix the work flow in xenon_remove(). MIPS: Octeon: cavium_octeon_defconfig: Enable Octeon MMC mmc: sdhci-xenon: Remove redundant dev_err call in get_dt_pad_ctrl_data() mmc: cavium: Use module_pci_driver to simplify the code mmc: cavium: Add MMC support for Octeon SOCs. mmc: cavium: Fix detection of block or byte addressing. mmc: core: Export API to allow hosts to get the card address mmc: sdio: Fix sdio wait busy implement limitation mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card clk: apn806: fix spelling mistake: "mising" -> "missing" mmc: sdhci-of-esdhc: add delay between tuning cycles mmc: sdhci: Control the delay between tuning commands mmc: sdhci-of-esdhc: add tuning support mmc: sdhci-of-esdhc: add support for signal voltage switch mmc: sdhci-of-esdhc: add peripheral clock support mmc: sdhci-pci: Allow for 3 bytes from Intel DSM mmc: cavium: Fix a shift wrapping bug ...
| * | mmc: sdhci-of-esdhc: limit SD clock for ls1012a/ls1046ayangbo lu2017-04-281-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ls1046a datasheet specified that the max SD clock frequency for eSDHC SDR104/HS200 was 167MHz, and the ls1012a datasheet specified it's 125MHz for ls1012a. So this patch is to add the limitation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-of-esdhc: poll ESDHC_CLOCK_STABLE bit with udelayyangbo lu2017-04-281-5/+4Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop to poll ESDHC_CLOCK_STABLE bit with mdelay would waste time because the time to stabilize is much less than 1 ms. This patch is to use udelay instead to avoid time wasting. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-xenon: Fix default value of LOGIC_TIMING_ADJUST for eMMC5.0 PHYHu Ziji2017-04-281-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default value of LOGIC_TIMING_ADJUST register in eMMC 5.0 PHY is different from that in eMMC 5.1 PHY. Set the specific value for that register in eMMC 5.0 PHY. Signed-off-by: Hu Ziji <huziji@marvell.com> Reported-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-xenon: Fix the work flow in xenon_remove().Hu Ziji2017-04-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sdhci_remove_host() might execute SOFT_RESET_ALL. Inside xenon_remove(), Xenon SDHC should be enabled during sdhci_remove_host(). Move xenon_sdhc_unprepare after sdhci_remove_host() such that Xenon SDHC is disabled after sdhci_remove_host() completes. Signed-off-by: Hu Ziji <huziji@marvell.com> Reported-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-xenon: Remove redundant dev_err call in get_dt_pad_ctrl_data()Wei Yongjun2017-04-251-4/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Use module_pci_driver to simplify the codeWei Yongjun2017-04-251-12/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the module_pci_driver() macro to make the code simpler by eliminating module_init and module_exit calls. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Add MMC support for Octeon SOCs.Steven J. Hill2017-04-243-0/+363
| | | | | | | | | | | | | | | | | | | | | | | | Add platform driver for Octeon SOCs. Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Fix detection of block or byte addressing.Steven J. Hill2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the mmc_card_is_blockaddr() function to properly detect if the card uses byte or block addressing. Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: Export API to allow hosts to get the card addressUlf Hansson2017-04-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some hosts controllers, like Cavium, needs to know whether the card operates in byte- or block-address mode. Therefore export a new API, mmc_card_is_blockaddr(), which provides this information. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Acked-by: David Daney <david.daney@cavium.com>
| * | mmc: sdio: Fix sdio wait busy implement limitationjiajie.hao@mediatek.com2017-04-242-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The host may issue an I/O abort by writing to the CCCR at any time during I/O read operation via CMD52. And host may need suspend transcation during write busy stage in SDIO suspend/resume scenario. >From other side, a card may accept CMD52 during data transfer phase. Previous implement would block issuing above command in busy stage. It cause function driver can't implement as proper way and has no opportunity to do some coverage in error case via I/O abort etc. We need bypass some necessary operation during busy check stage. Signed-off-by: Jiajie Hao <jiajie.hao@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc cardHaibo Chen2017-04-241-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USDHC tuning circuit should be reset before every time card enumeration or re-enumeration. SD3.0 card need tuning. For SDR104 card, when system suspend in standby mode, and then resume back, the IO timing is still SDR104(tuned) which may result in card re-enumeration fail in low card speed(400khz) for some cards. And we did meet the issue that in certain probability, SDR104 card meet mmc command CRC/Timeout error when send CMD2 during mmc bus resume. This patch reset the tuning circuit when the ios timing is MMC_TIMING_LEGACY/MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS, which means both mmc_power_up() and mmc_power_off() will reset the tuning circuit. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-of-esdhc: add delay between tuning cyclesyangbo lu2017-04-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's observed that eSDHC needed delay between tuning cycles for HS200 successful tuning. This patch is to set 1ms delay for that. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci: Control the delay between tuning commandsAdrian Hunter2017-04-242-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The delay between tuning commands for SD cards is not part of the specification. A driver that needs it probably needs it for eMMC too, whereas most drivers would probably like to set it to 0. Make it a host member (host->tuning_delay) that defaults to the existing behaviour. Drivers can set it to zero to eliminate the delay, or set it to a positive value to always have a delay. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-of-esdhc: add tuning supportyangbo lu2017-04-242-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-of-esdhc: add support for signal voltage switchyangbo lu2017-04-242-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-of-esdhc: add peripheral clock supportyangbo lu2017-04-242-2/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-pci: Allow for 3 bytes from Intel DSMAdrian Hunter2017-04-241-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | The DSM used by some Intel controllers can return a 3 byte package. Allow for that by using memcpy to copy the bytes. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Fix a shift wrapping bugDan Carpenter2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | "dat" is a u64 and "shift" starts as 54 so this is a shift wrapping bug. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Check pointer before de-referenceJan Glauber2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pointer check to prevent this smatch warning: drivers/mmc/host/cavium.c:803 cvm_mmc_request() error: we previously assumed 'cmd->data' could be null (see line 782) This is a theoretical fix because MMC_CMD_ADTC seems to imply that cmd->data is not null. Nevertheless checking cmd->data before using it improves readability. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Remove redundant pointer checkJan Glauber2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove redundant mmc->card check reported by smatch: drivers/mmc/host/cavium.c:694 cvm_mmc_dma_request() warn: variable dereferenced before check 'mmc->card' (see line 675) Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: meson-gx: add support for descriptor chain modeHeiner Kallweit2017-04-241-16/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far a bounce buffer is used to serialize the scatterlist(s). This overhead can be avoided by switching to descriptor chain mode. As result the performance is drastically improved. On a Odroid-C2 with a 128 GB eMMC module raw reads reach 140 MB/s. Prerequisite for descriptor chain mode is that all scatterlist buffers are 8 byte aligned for 64-bit DMA. That's not always the case, at least the brcmfmac SDIO WiFi driver is known to cause problems. Therefore, for each request, check upfront whether all scatterlist buffers are 8 byte aligned and fall back to bounce buffer mode if that's not the case. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: meson-gx: add basic tuning for rx clock phaseHeiner Kallweit2017-04-241-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic tuning which changes the rx clock phase only until a working setting is found. On a Odroid C2 with 128GB eMMC card and 200 MHz MMC clock only 180° rx clock phase make the system boot w/o CRC errors. With other MMC devices / clock speeds this might be different, therefore don't change the driver config in general. When retuning skip the currently active parameter set. This avoids the current problematic config to be chosen again if it causes CRC errors just occasionally. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: meson-gx: introduce struct meson_tuning_paramsHeiner Kallweit2017-04-241-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce struct meson_tuning_params for storing the clock phase configurations. There's no functional change because tx and rx clock phase were implicitely set to CLK_PHASE_0 before. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: add proper be32 annotationWinkler, Tomas2017-04-244-17/+16Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | Annotate big endian values correctly and make sparse happy. In mmc_app_send_scr remove scr function parameter as it was updating card->raw_scr anyway. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-cadence: add parsing sdhci propertiesPiotr Sroka2017-04-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add calling sdhci_get_of_property function to parse sdhci properties. Signed-off-by: Piotr Sroka <piotrs@cadence.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: host: omap_hsmmc: checking for NULL instead of IS_ERR()Dan Carpenter2017-04-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | devm_pinctrl_get() returns error pointers, it never returns NULL. Fixes: 455e5cd6f736 ("mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-xenon: Add SoC PHY PAD voltage controlHu Ziji2017-04-243-1/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs have PHY PAD outside Xenon IP. PHY PAD voltage should match signalling voltage in use. Add generic SoC PHY PAD voltage control interface. Implement Aramda-3700 SoC PHY PAD voltage control. Signed-off-by: Hu Ziji <huziji@marvell.com> Tested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHCHu Ziji2017-04-244-3/+774
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY. Multiple types of PHYs are supported. Add support to multiple types of PHYs init and configuration. Add register definitions of PHYs. Xenon PHY cannot fit in kernel common PHY framework. Xenon SDHC PHY register is a part of Xenon SDHC register set. Besides, MMC initialization has to call several PHY functions to complete timing setting. Those PHY setting functions have to access SDHC registers and know current MMC setting, such as bus width, clock frequency and speed mode. As a result, implement Xenon PHY in MMC host directory. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionalityHu Ziji2017-04-244-0/+612
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Xenon eMMC/SD/SDIO host controller core functionality. Add Xenon specific initialization process. Add Xenon specific mmc_host_ops APIs. Add Xenon specific register definitions. Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig. Marvell Xenon SDHC conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.cHu Ziji2017-04-242-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC driver can implement its specific SDIO irq control. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.cHu Ziji2017-04-242-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export sdhci_start_signal_voltage_switch() from sdhci.c. Thus vendor sdhci driver can implement its own signal voltage switch routine. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: sdhci: Export sdhci_set_ios() from sdhci.cHu Ziji2017-04-242-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export sdhci_set_ios() in sdhci.c. Thus vendor sdhci driver can implement its own set_ios() routine. Signed-off-by: Hu Ziji <huziji@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Support DDR mode for eMMC devicesJan Glauber2017-04-241-1/+11
| | | | | | | | | | | | | | | | | | | | | Add support for switching to DDR mode for eMMC devices. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Add scatter-gather DMA supportJan Glauber2017-04-243-10/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Support for the scatter-gather DMA available in the ThunderX MMC units. Up to 16 DMA requests can be processed together. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Add MMC PCI driver for ThunderX SOCsJan Glauber2017-04-244-0/+215
| | | | | | | | | | | | | | | | | | | | | Add a platform driver for ThunderX ARM SOCs. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: cavium: Add core MMC driver for Cavium SOCsJan Glauber2017-04-242-0/+1174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This core driver will be used by a MIPS platform driver or by an ARM64 PCI driver. The core driver implements the mmc_host_ops and slot probe & remove functions. Callbacks are provided to allow platform specific interrupt enable and bus locking. The host controller supports: - up to 4 slots that can contain sd-cards or eMMC chips - 1, 4 and 8 bit bus width - SDR and DDR - transfers up to 52 Mhz (might be less when multiple slots are used) - DMA read/write - multi-block read/write (but not stream mode) Voltage is limited to 3.3v and shared for all slots (vmmc and vmmcq). A global lock for all MMC devices is required because the host controller is shared. Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Steven J. Hill <steven.hill@cavium.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: refactor mmc_request_done()Linus Walleij2017-04-241-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have this construction: if (a && b && !c) finalize; else block; finalize; Which is equivalent by boolean logic to: if (!a || !b || c) block; finalize; Which is simpler code. Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: refactor asynchronous request finalizationLinus Walleij2017-04-241-53/+33Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_wait_for_data_req_done() is called in exactly one place, and having it spread out is making things hard to oversee. Factor this function into mmc_finalize_areq(). Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: move some code in mmc_start_areq()Linus Walleij2017-04-241-8/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "previous" is a better name for the variable storing the previous asynchronous request, better than the opaque name "data" atleast. We see that we assign the return status to the returned variable on all code paths, so we might as well just do that immediately after calling mmc_finalize_areq(). Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: Factor out mrq preparation from mmc_start_request()Adrian Hunter2017-04-241-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | In preparation to reuse the code for CQE support. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: core: Factor out debug prints from mmc_start_request()Adrian Hunter2017-04-241-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | In preparation to reuse the code for CQE support. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: block: Factor out data preparationAdrian Hunter2017-04-241-69/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out data preparation into a separate function mmc_blk_data_prep() which can be re-used for command queuing. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: block: Change mmc_apply_rel_rw() to get block address from the requestAdrian Hunter2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_apply_rel_rw() will be used by Software Command Queuing also. In that case the command argument is not the block address so change mmc_apply_rel_rw() to get block address from the request. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: block: Disable Command Queue while RPMB is usedAdrian Hunter2017-04-241-8/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RPMB does not allow Command Queue commands. Disable and re-enable the Command Queue when switching. Note that the driver only switches partitions when the queue is empty. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Harjani Ritesh <riteshh@codeaurora.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: mmc_test: Disable Command Queue while mmc_test is usedAdrian Hunter2017-04-242-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normal read and write commands may not be used while the command queue is enabled. Disable the Command Queue when mmc_test is probed and re-enable it when it is removed. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Harjani Ritesh <riteshh@codeaurora.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | mmc: mmc: Add functions to enable / disable the Command QueueAdrian Hunter2017-04-243-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add helper functions to enable or disable the Command Queue. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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