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* mmc: tmio: enable odd number size accessKuninori Morimoto2014-09-191-4/+35
| | | | | | | | | | | | | | Current tmio is using sd_ctrl_read16/write16_rep() for data transfer. It works if transfer size was even number, but, last 1 byte will be ignored if transfer size was odd number. This patch adds new tmio_mmc_transfer_data() and solve this issue. Tested-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: block: change stop errors to infoJohan Rudholm2014-09-191-1/+1
| | | | | | | | | Stop command errors are not fatal to the transfer since we make sure that the card returns to the transfer state and check the card status. Change an unnecessary error to an info. Signed-off-by: Johan Rudholm <johanru@axis.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: Remove unused function for !CONFIG_OFTobias Klauser2014-09-191-4/+0Star
| | | | | | | | | | | | dw_mci_of_find_slot_node() is only used in dw_mci_of_get_slot_quirks() if CONFIG_OF is defined, thus there is no need to have a !CONFIG_OF version of it. Fixes the following compile warning with !CONFIG_OF: CC [M] drivers/mmc/host/dw_mmc.o drivers/mmc/host/dw_mmc.c:2223:28: warning: ‘dw_mci_of_find_slot_node’ defined but not used [-Wunused-function] Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: Checks EXT_CSD_PARTITION_SETTING_COMPLETED before partitions computationGrégory Soutadé2014-09-191-37/+44
| | | | | | | | | | | | Checks EXT_CSD_PARTITION_SETTING_COMPLETED bit before computing enhanced user area offset and size, and adding mmc general purpose partitions. The two needs EXT_CSD_PARTITION_SETTING_COMPLETED bit be set to be valid (as described in JEDEC standard). Warn user in case of misconfiguration. Signed-off-by: Grégory Soutadé <gsoutade@neotion.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: Replace "enhanced_area_en" attribute by "partition_setting_completed"Grégory Soutadé2014-09-191-5/+8
| | | | | | | | | | Replace ext_csd "enhanced_area_en" attribute by "partition_setting_completed". It was used whether or not enhanced user area is defined and without checks of EXT_CSD_PARTITION_SETTING_COMPLETED bit. Signed-off-by: Grégory Soutadé <gsoutade@neotion.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: Move code that manages user area and gp partitions into functionsGrégory Soutadé2014-09-191-73/+89
| | | | | | | | Move code that manages user area and general purpose partitions into functions. Signed-off-by: Grégory Soutadé <gsoutade@neotion.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pxav3: fix error handling of sdhci_add_hostXiang Wang2014-09-101-2/+2
| | | | | | | | | | Commit 0dcaa2499b7d111bd70da5b0976c34210c850fb3 improved error handling of sdhci_add_host. However, "err_of_parse" and "err_cd_req" should be placed after "pm_runtime_disable(&pdev->dev)". Signed-off-by: Xiang Wang <wangx@marvell.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: rename sdio flag in vendor data to st_sdioSrinivas Kandagatla2014-09-101-24/+24
| | | | | | | | | | | | This patch renames sdio flag in vendor data to st_sdio, as this flag is only used to enable ST specific sdio setup. This will also ensure that the ST specfic setup is not done on other vendor like Qualcomm. Originally the issue was detected while testing WLAN ath6kl on IFC6410 board with APQ8064 SOC. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: Add sdio enable mask in variant dataSrinivas Kandagatla2014-09-101-7/+7
| | | | | | | | | | | | | | | This patch adds sdio enable mask in variant data, SOCs like ST have special bits in datactrl register to enable sdio. Unconditionally setting this bit in this driver breaks other SOCs like Qualcomm which maps this bits to something else, so making this enable bit to come from variant data solves the issue. Originally the issue is detected while testing WLAN ath6kl on Qualcomm APQ8064. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: mmci: augment driver to handle gpio descriptorsLinus Walleij2014-09-091-10/+29
| | | | | | | | | | | | | | | | | | | | | | Currently the MMCI driver will only handle GPIO descriptors implicitly through the device tree probe glue in mmc_of_init(), but devices instatiated other ways such as through board files and passing descriptors using the GPIO descriptor table will not be able to exploit descriptors. Augment the driver to look for a GPIO descriptor if device tree is not used for the device, and if that doesn't work, fall back to platform data GPIO assignment using the old API. The end goal is to get rid of the platform data integer GPIO assingments from the kernel. This enable the MMCI-embedding platforms to be converted to GPIO descritor tables. Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: host: switch OF parser to use gpio descriptorsLinus Walleij2014-09-091-45/+23Star
| | | | | | | | | | | | This switches the central MMC OF parser to use gpio descriptors instead of grabbing GPIOs explicitly from the device tree. This strips out an unecessary use of the integer-based GPIO API that we want to get rid of, cuts down on code as the gpio descriptor code will handle active low flags. Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: slot-gpio: add gpiod variant to get wp GPIOLinus Walleij2014-09-091-0/+48
| | | | | | | | | | This makes it possible to get the write protect (read only) GPIO line from a GPIO descriptor. Written to exactly mirror the card detect function. Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: slot-gpio: switch to use flags when getting GPIOLinus Walleij2014-09-091-5/+1Star
| | | | | | | | | | | | | | | When the slot GPIO driver gets the GPIO to be used for card detect, it is now possible to specify a flag to have the line set up as input. Get rid of the explicit setup call for input and use the flag. The extra argument works as there are transition varargs macros in place in the <linux/gpio/consumer.h> header, in the future we will make the flags argument compulsory. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: card: Prevent partition scan for the eMMC boot areasUlf Hansson2014-09-091-1/+1
| | | | | | | | It seems very unlikely that eMMC devices would hold a standard partitiontable in one of it's boot areas. Therefore, let's prevent them from being scanned. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: remove MMC_CAP2_NO_MULTI_READ flagsKuninori Morimoto2014-09-091-5/+0Star
| | | | | | | | | Now, mmc framework uses multi_io_quirk for I/O HW bug workaround. MMC_CAP2_NO_MULTI_READ flag is no longer needed Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: use .multi_io_quirk on sh_mobileKuninori Morimoto2014-09-091-1/+19
| | | | | | | | | Now, sh_mobile_sdhi can use .multi_io_quirk callback instead of MMC_CAP2_NO_MULTI_READ flags. let's use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: use .multi_io_quirk on tmio_mmcKuninori Morimoto2014-09-091-0/+13
| | | | | | | | | | Now, tmio_mmc can use .multi_io_quirk callback instead of MMC_CAP2_NO_MULTI_READ flags. let's use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: use .multi_io_quirk on omap_hsmmcKuninori Morimoto2014-09-091-2/+12
| | | | | | | | | Now, omap_hsmmc can use .multi_io_quirk callback instead of MMC_CAP2_NO_MULTI_READ flags. let's use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: disable preset register for Baytrail and MerrifieldGao, Yunpeng2014-09-091-3/+6
| | | | | | | | | | Due to HW issue, SDHCI host controller on Intel Baytrail/Merrifield platforms can not use preset register. So, disable preset registers for them by quirks. Signed-off-by: Yunpeng Gao <yunpeng.gao@intel.com> Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: Add .multi_io_quirk callback for multi I/O HW bugKuninori Morimoto2014-09-091-0/+10
| | | | | | | | | | | | | | | | Historically, we have been using MMC_CAP* to handle host HW issues and currently the block layer uses MMC_CAP2_NO_MULTI_READ flag for a multi I/O HW bug workaround. There are a few tweaks needed to make MMC_CAP2_NO_MULTI_READ suite all situations. Therefore let's add an optional host ops callback to enable host drivers to return the number of blocks it allows per request. In a future patch and when host drivers have converted to the new callback, MMC_CAP2_NO_MULTI_READ shall be removed. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: check 1.2v IO capability for SDHC hostChuanxiao.Dong2014-09-091-1/+6
| | | | | | | | | | | | | Right now enable 1.2v IO voltage for SDHC is by using vqmmc. Thus for the host which doesn't have vqmmc, or its vqmmc does not support 1.2v, directly use MMC_CAP2_HS200 may cause HS200 failure. So needs to check if vqmmc is able to support 1.2v. If it does not support, disable 1.2v IO for HS200. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: Fix sequence for I/O voltage in DDR mode for eMMCChuanxiao.Dong2014-09-091-9/+25
| | | | | | | | | | | | | | | | | | | Even (e)MMC card can support 3.3v to 1.2v vccq in DDR, but not all host controller can support this, like some of the SDHCI host which connect to an eMMC device. Some of these host controller still needs to use 1.8v vccq for supporting DDR mode. So the sequence will be: if (host and device can both support 1.2v IO) use 1.2v IO; else if (host and device can both support 1.8v IO) use 1.8v IO; so if host and device can only support 3.3v IO, this is the last choice. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Yunpeng Gao <yunpeng.gao@intel.com> Tested-by: Jean-Michel Hautbois <jhautbois@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: pxamci: prepare and unprepare the clocksRobert Jarzmik2014-09-091-2/+2
| | | | | | | | | Add the clock prepare and unprepare call to the driver set_ios calls phase. This will remove a warning once the PXA architecture is migrated to the clock infrastructure. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-acpi: add probe_slot method for emmc/sd/sdioGao, Yunpeng2014-09-091-0/+58
| | | | | | | | | Similar to sdhci-pci controller, also add probe_slot and remove_slot method in the sdhci-acpi driver. Signed-off-by: Yunpeng Gao <yunpeng.gao@intel.com> Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-pci: enable runtime pm for Intel Merrifield platformGao, Yunpeng2014-09-091-0/+1
| | | | | | | Enable runtime pm support on Intel Merrifield platform. Signed-off-by: Yunpeng Gao <yunpeng.gao@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: handle busy-end interrupt during commandChanho Min2014-09-091-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is fully legal for a controller to start handling busy-end interrupt before it has signaled that the command has completed. So make sure we do things in the proper order, Or it results that command interrupt is ignored so it can cause unexpected operations. This is founded at some toshiba emmc with the bellow warning. "mmc0: Got command interrupt 0x00000001 even though no command operation was in progress." This issue has been also reported by Youssef TRIKI: It is not specific to Toshiba devices, and happens with eMMC devices as well as SD card which support Auto-CMD12 rather than CMD23. Also, similar patch is submitted by: Gwendal Grignou <gwendal@chromium.org> Changes since v1: Fixed conflict with the next of git.linaro.org/people/ulf.hansson/mmc.git and Tested if issue is fixed again. Signed-off-by: Hankyung Yu <hankyung.yu@lge.com> Signed-off-by: Chanho Min <chanho.min@lge.com> Tested-by: Youssef TRIKI <youssef.triki@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* sdhci: Make sdhci_disable_irq_wakeups() staticFabio Estevam2014-09-091-2/+1Star
| | | | | | | | | | | | sdhci_disable_irq_wakeups() is exported, but it is not called outside sdhci.c. Make it static and do not export it, so that the following sparse warning is fixed: drivers/mmc/host/sdhci.c:2548:6: warning: symbol 'sdhci_disable_irq_wakeups' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: move timeout_clk dynamically calculation code into common codeAisheng Dong2014-09-091-11/+13
| | | | | | | | | The timeout_clk calculation code for SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK case is common and could be moved into common sdhci_do_set_ios, then platform code which is not using sdhci_set_clock does not need to write the same code again. Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: calculate timeout_clk conditionally in sdhci_add_hostAisheng Dong2014-09-091-17/+17
| | | | | | | | | The timeout_clk calculation code in sdhci_add_host is meaningless for SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK. So only execute them with no SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK set. Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-esdhc-imx: set the correct max timeout value for uSDHCAisheng Dong2014-09-091-0/+11
| | | | | | | | | | | | | | | | The default sdhci driver write 0xE into timeout counter register to set the maximum timeout. The value is not correct for uSDHC since the max counter value for uSDHC is 0xF. Instead of using common timeout code in sdhci, we implement esdhc_set_timeout to handle the difference between eSDHC and uSDHC. Currently we simply set the max timeout value as before. But in the future, we probably may implement IMX specific timeout setting algorithm and use suitable timeout for different CMDs. Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: add platform set_timeout hookAisheng Dong2014-09-092-5/+16
| | | | | | | | | | | | | | | | Currently the common code assume 0xE is the maximum timeout counter value and use it to write into the timeout counter register. However, it's fairly possible that some other SoCs may have different max timeout register value. That means 0xE may be incorrect and becomes meaningless. It's also possible that other platforms has different timeout calculation algorithm. To be flexible, this patch provides a .set_timeout hook for those platforms to set the timeout on their way if they need. Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-esdhc-imx: fix incorrect max timeout cout for uSDHCAisheng Dong2014-09-091-0/+9
| | | | | | | | | | | The default sdhci code use the 1 << 27 as the max timeout counter to to calculate the max_busy_timeout, however it's not correct for uSDHC since its the max counter is 1 << 28. Implement esdhc_get_max_timeout_cout to handle it correctly. Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: add platform get_max_timeout_count hookAisheng Dong2014-09-092-2/+8
| | | | | | | | | | | | | | | Currently the max timeout count is hardcode to 1 << 27 for calcuate the max_busy_timeout, however, for some platforms the max timeout count may not be 1 << 27, e.g. i.MX uSDHC is 1 << 28. Thus 1 << 27 is not correct for such platform. It is also possible that other platforms may have different values. To be flexible, we add a get_max_timeout_count hook to get the correct maximum timeout value for these platforms. Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio-mmc: Add support for SDHI on new R-Car Gen2 SoCsGeert Uytterhoeven2014-09-091-0/+3
| | | | | | | | | - r8a7792 (R-Car V2H) - r8a7793 (R-Car M2-N) - r8a7794 (R-Car E2) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: Pass back errors from mmc_of_parse()Doug Anderson2014-09-091-4/+6
| | | | | | | | | | It's possible that mmc_of_parse() could return errors (possibly in some future version it might return -EPROBE_DEFER even). Let's pass those errors back. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci-sirf: fix 8bit width enable by overwriting set_bus_widthMinda Chen2014-09-091-1/+23
| | | | | | | | | | | | | | | the implementation of CSR SDHCI controller is a modified version of the one described in the 1.0 specification, and not a normal 3.0 controller. and 8bit-width enable bit of CSR MMC hosts is 3, while stardard hosts use bit 5. this patch fixes the functionality of 8bit transfer in mmc controllers and improve performance for mmc0 a lot. Signed-off-by: Minda Chen <Minda.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Romain Izard <romain.izard.pro@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: Support voltage changesDoug Anderson2014-09-092-10/+132
| | | | | | | | | | | | For UHS cards we need the ability to switch voltages from 3.3V to 1.8V. Add support to the dw_mmc driver to handle this. Note that dw_mmc needs a little bit of extra code since the interface needs a special bit programmed to the CMD register while CMD11 is progressing. This means adding a few extra states to the state machine to track. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: use mmc_regulator_get_supply to handle regulatorsYuvaraj CD2014-09-091-37/+35Star
| | | | | | | | | | | This patch makes use of mmc_regulator_get_supply() to handle the vmmc and vqmmc regulators.Also it moves the code handling the these regulators to dw_mci_set_ios().It turned on the vmmc and vqmmc during MMC_POWER_UP and MMC_POWER_ON,and turned off during MMC_POWER_OFF. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: core: resolve divded by zero panicChuanxiao Dong2014-09-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With one special SD card, below divide by zero error observed: ... [ 2.144300] divide error: 0000 [#1] PREEMPT SMP [ 2.148860] Modules linked in: [ 2.151898] [ 2.152685] Set up 4031 stolen pages starting at 0x0001f000, GTT offset 0K [ 2.157330] Set up 0 CI stolen pages starting at 0x00000000, GTT offset 131072K [ 2.167581] Pid: 5, comm: kworker/u:0 Not tainted 3.0.8-138216-g974a2ab #1 [ 2.169506] [drm] PSB GTT mem manager ready, tt_start 4031, tt_size 28737 pages [ 2.169906] [drm] SGX core id = 0x00000000 [ 2.169920] [drm] SGX core rev major = 0x00, minor = 0x00 [ 2.169934] [drm] SGX core rev maintenance = 0x00, designer = 0x00 [ 2.197370] Intel Corporation Medfield/iCDKB [ 2.201716] EIP: 0060:[<c1697ca6>] EFLAGS: 00010246 CPU: 1 [ 2.207198] EIP is at mmc_init_erase+0x76/0x150 [ 2.211704] EAX: 00002000 EBX: dcd1b400 ECX: 00002000 EDX: 00000000 [ 2.217957] ESI: 00000000 EDI: dcd5c800 EBP: dd867e84 ESP: dd867e7c [ 2.224214] DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068 [ 2.229605] Process kworker/u:0 (pid: 5, ti=dd866000 task=dd868000 task.ti=dd866000) [ 2.237325] Stack: [ 2.239322] dcd1b400 00000000 dd867eb0 c16a06da c1ab7c44 dd995aa8 00000003 00000000 [ 2.247054] 00000000 00000000 dcd5c800 00000000 dcd1b400 dd867ef8 c16a1012 c1698b00 [ 2.254785] 00000029 00000001 c194eb80 dcd5c9ec dd867e00 c1239b00 00000000 00000000 [ 2.262519] Call Trace: [ 2.264975] [<c16a06da>] mmc_sd_setup_card+0x1da/0x4f0 [ 2.270183] [<c16a1012>] mmc_sd_init_card+0x192/0xc40 [ 2.275304] [<c1698b00>] ? __mmc_claim_host+0x160/0x160 [ 2.280610] [<c1239b00>] ? __schedule_bug+0x50/0x80 [ 2.285556] [<c16a1b89>] mmc_attach_sd+0xc9/0x230 [ 2.290333] [<c169b6ef>] mmc_rescan+0x25f/0x2c0 [ 2.294943] [<c1274223>] process_one_work+0x103/0x400 [ 2.300065] [<c12670fd>] ? mod_timer+0x1ad/0x3c0 [ 2.304756] [<c169b490>] ? mmc_suspend_host+0x1a0/0x1a0 [ 2.310056] [<c127502d>] worker_thread+0x12d/0x4a0 [ 2.314921] [<c18fcfbd>] ? preempt_schedule+0x2d/0x50 [ 2.320047] [<c1274f00[ 2.323976] ---[ end trace 5398ec2720494438 ]--- ... So, seems this bad SD card does not set valid value in related SSR / CSD register fields. And then the driver will set card->erase_size to 0. Then it triggered this divided by zero error when calculate card->pref_erase. Submit this patch to fix the issue. Signed-off-by: Yunpeng Gao <yunpeng.gao@intel.com> Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sunxi: Declare ERASE capabilityChen-Yu Tsai2014-09-091-1/+2
| | | | | | | | | Declare ERASE capability so we can use filesystems with the discard option and the fstrim tool. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: sdhci: Add PCI IDs for Intel BraswellAlan Cox2014-09-092-0/+26
| | | | | | | | | The hardware is the same as used in Baytrail. Add these new PCI IDs to the driver's list of supported IDs. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: dw_mmc: move rockchip related code to a separate fileaddy ke2014-09-094-57/+146
| | | | | | | | | | | | To support HS200 and UHS-1, we need add a big hunk of code, as shown in the following patches. So a separate file for rockchip SOCs is suitable. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: add actual clock support as optionShinobu Uehara2014-09-092-2/+9
| | | | | | | | | | | | | | | Some controller is supporting actual clock on SD_CLK_CTRL :: DIV[7:0]. Renesas SH-Mobile SDHI doesn't support, but, Renesas R-Car SDHI supports it. This patch adds new TMIO_MMC_CLK_ACTUAL flag for it. [Kuninori Morimoto: tidyuped for upstreaming] Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: remove SCLKEN bit setting from tmio_mmc_set_clock()Kuninori Morimoto2014-09-091-1/+0Star
| | | | | | | | | | | | | TMIO clock is set via tmio_mmc_set_clock() -> tmio_mmc_clk_start(), and SCLKEN bit will be set on tmio_mmc_clk_start(). It is not needed on tmio_mmc_set_clock() function. The required clock setting will not be able to set in some clocks without this patch. Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: remove Renesas specific #ifdefKuninori Morimoto2014-09-092-4/+7
| | | | | | | | | | This patch adds new TMIO_MMC_HAVE_CTL_DMA_REG flag, and remove Renesas specific #ifdef from tmio driver Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: check ILL_FUNC instead of CBSYShinobu Uehara2014-09-091-1/+12
| | | | | | | | | | | | | | | | | | | | | Some controllers need to check SD bus status when writing data. Then, it checks ILL_FUNC bit on SD_INFO2 register, and this method is controlled via TMIO_MMC_HAS_IDLE_WAIT flags. Same method is required on tmio_mmc_data_irq() which will be called after writing data. Current driver is checking CBSY bit for this purpose, but, some controllers doesn't have CBSY bit. This patch checks ILL_FUNC bit instead of CBSY bit if it has TMIO_MMC_HAS_IDLE_WAIT flags [Kuninori Morimoto: tidyuped for upstreaming] Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: add TMIO_MMC_SDIO_STATUS_QUIRKShinobu Uehara2014-09-092-1/+11
| | | | | | | | | | | | | | | | Renesas R-Car SDHI should set reserved bits on CTL_SDIO_STATUS register when writing. This patch adds new TMIO_MMC_SDIO_STATUS_QUIRK flags for this purpose [Kuninori Morimoto: tidyuped for upstreaming enabled this flags for all SH-Mobile/R-Car] Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: control multiple block transfer modeShinobu Uehara2014-09-092-0/+15
| | | | | | | | | | | | | | | | | Renesas SDHI has "Multiple Block Transfer Mode" settings on SD_CMD register which controls CMD12 automatically. This patch cares it, because CMD12 is not needed when CMD53 (= SD_IO_RW_EXTENDED) [Kuninori Morimoto: tidyuped for upstreaming enabled this flags for all SH-Mobile/R-Car] Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: clear error IRQ statusShinobu Uehara2014-09-091-0/+3
| | | | | | | | | | | Next card access will be always error if it didn't clear error status Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* mmc: tmio: care about DMA tx/rx addr offsetKuninori Morimoto2014-09-092-1/+4
| | | | | | | | | | | | | | | | | Basically, SD_BUF0 Tx/Rx addresses are same in normal TMIO controller, but, it is different on Renesas R-Car SDHI controller if it uses DMAC (Rx address needs to add 0x2000 to Tx address) This patch adds new .dma_rx_offset and cares it Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-12 11:45:18 +0200