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* Merge branch 'pci/trivial'Bjorn Helgaas2019-07-132-2/+2
|\ | | | | | | | | | | | | - Fix typos and whitespace errors (Bjorn Helgaas) * pci/trivial: PCI: Fix typos and whitespace errors
| * PCI: Fix typos and whitespace errorsBjorn Helgaas2019-07-092-2/+2
| | | | | | | | | | | | | | | | Fix typos in drivers/pci. Comment and whitespace changes only. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
* | Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas2019-07-131-61/+54Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move qcom driver to bulk clock API (Bjorn Andersson) - Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson) - Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel) * remotes/lorenzo/pci/qcom: PCI: qcom: Ensure that PERST is asserted for at least 100 ms PCI: qcom: Add QCS404 PCIe controller support dt-bindings: PCI: qcom: Add QCS404 to the binding PCI: qcom: Use clk bulk API for 2.4.0 controllers
| * | PCI: qcom: Ensure that PERST is asserted for at least 100 msNiklas Cassel2019-05-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, there is only a 1 ms sleep after asserting PERST. Reading the datasheets for different endpoints, some require PERST to be asserted for 10 ms in order for the endpoint to perform a reset, others require it to be asserted for 50 ms. Several SoCs using this driver uses PCIe Mini Card, where we don't know what endpoint will be plugged in. The PCI Express Card Electromechanical Specification r2.0, section 2.2, "PERST# Signal" specifies: "On power up, the deassertion of PERST# is delayed 100 ms (TPVPERL) from the power rails achieving specified operating limits." Add a sleep of 100 ms before deasserting PERST, in order to ensure that we are compliant with the spec. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: stable@vger.kernel.org # 4.5+
| * | PCI: qcom: Add QCS404 PCIe controller supportBjorn Andersson2019-05-291-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QCS404 platform contains a PCIe version 2.4.0 controller and a Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the IPQ4019, but this support touches clocks and resets related to the PHY as well and there's no upstream driver for the PHY. On QCS404 we must initialize the PHY, so a separate PHY driver is implemented to take care of this and the controller driver is updated to not require the PHY related resources. This is done by relying on the fact that operations in both the clock and reset framework are NOPs when passed NULL, so we can isolate this change to only the qcom_pcie_get_resources_2_4_0() function. For QCS404 we also need to enable the AHB (iface) clock, in order to access the register space of the controller, but as this is not part of the IPQ4019 DT binding this is only added for new users of the 2.4.0 controller. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| * | PCI: qcom: Use clk bulk API for 2.4.0 controllersBjorn Andersson2019-05-291-37/+16Star
| |/ | | | | | | | | | | | | | | | | | | | | | | Before introducing the QCS404 platform, which uses the same PCIe controller as IPQ4019, migrate this to use the bulk clock API, in order to make the error paths slighly cleaner. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-07-135-35/+80
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add dwc API support to de-initialize host (Vidya Sagar) - Clean up dwc DBI,ATU read and write APIs (Vidya Sagar) - Export dwc APIs to support .remove() so drivers can be modular (Vidya Sagar) - Simplify imx6 Kconfig dependencies (Leonard Crestez) - Fix dra7xx build error when !CONFIG_GPIOLIB (YueHaibing) * remotes/lorenzo/pci/dwc: PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB PCI: imx6: Simplify Kconfig depends on PCI: dwc: Export APIs to support .remove() implementation PCI: dwc: Cleanup DBI,ATU read and write APIs PCI: dwc: Add API support to de-initialize host
| * | PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIBYueHaibing2019-07-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_GPIOLIB is not selected the compilation results in the following build errors: drivers/pci/controller/dwc/pci-dra7xx.c: In function dra7xx_pcie_probe: drivers/pci/controller/dwc/pci-dra7xx.c:777:10: error: implicit declaration of function devm_gpiod_get_optional; did you mean devm_regulator_get_optional? [-Werror=implicit-function-declaration] reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); drivers/pci/controller/dwc/pci-dra7xx.c:778:45: error: ‘GPIOD_OUT_HIGH’ undeclared (first use in this function); did you mean ‘GPIOF_INIT_HIGH’? reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH); ^~~~~~~~~~~~~~ GPIOF_INIT_HIGH Fix them by including the appropriate header file. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | PCI: imx6: Simplify Kconfig depends onLeonard Crestez2019-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The imx6 driver can be used on imx6sx without enabling support for imx6q or imx7d but the "depends on" condition doesn't allow that. Instead of making the condition even longer just make it depend on "ARCH_MXC || COMPILE_TEST" instead. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Lucas Stach <l.stach@pengutronix.de>
| * | PCI: dwc: Export APIs to support .remove() implementationVidya Sagar2019-06-272-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export all configuration space access APIs and also other APIs to support host controller drivers of dwc core based implementations while adding support for .remove() hook to build their respective drivers as modules. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
| * | PCI: dwc: Cleanup DBI,ATU read and write APIsVidya Sagar2019-06-272-34/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleanup DBI read and write APIs by removing leading "__" (underscore) from their names as there is no reason to have leading underscores in the first place in the function definition. Remove dbi/dbi2 base address parameters as the same behaviour can be obtained through read and write APIs. Since dw_pcie_{readl/writel}_dbi() APIs can't be used for ATU read/write as ATU base address could be different from DBI base address, implement ATU read/write APIs using ATU base address without using dw_pcie_{readl/writel}_dbi() APIs. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
| * | PCI: dwc: Add API support to de-initialize hostVidya Sagar2019-06-272-0/+13
| |/ | | | | | | | | | | | | | | | | | | Add an API to group all the tasks to be done to de-initialize host which can then be called by any dwc core based driver implementations while adding .remove() support in their respective drivers. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
* / PCI: armada8k: Add PHYs supportMiquel Raynal2019-06-171-1/+81
|/ | | | | | | | | | | | | | | | Bring PHY support for the Armada8k driver. The Armada8k IP only supports x1, x2 or x4 link widths. Iterate over the DT 'phys' entries and configure them one by one. Use phy_set_mode_ext() to make use of the submode parameter (initially introduced for Ethernet modes). For PCI configuration, let the submode be the width (1, 2, 4, etc) so that the PHY driver knows how many lanes are bundled. Do not error out in case of error for compatibility reasons. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
* Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas2019-05-143-3/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Exit pcitest with error code when test fails (Jean-Jacques Hiblot) - Fix leaked of_node references in dra7xx, uniphier, layerscape, rockchip, aardvark, iproc, mediatek, rpadlpar (Wen Yang) - Fix pcitest "help" option parsing (Kishon Vijay Abraham I) - Fix Makefile bug that inadvertently removes pcitest.sh (Kishon Vijay Abraham I) - Check for alloc_workqueue() failure in endpoint test driver (Kangjie Lu) * remotes/lorenzo/pci/misc: PCI: endpoint: Fix a potential NULL pointer dereference tools: PCI: Handle pcitest.sh independently from pcitest tools: PCI: Add 'h' in optstring of getopt() PCI: mediatek: Fix a leaked reference by adding missing of_node_put() PCI: iproc: Fix a leaked reference by adding missing of_node_put() PCI: aardvark: Fix a leaked reference by adding missing of_node_put() PCI: rockchip: Fix a leaked reference by adding missing of_node_put() PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put() PCI: uniphier: Fix a leaked reference by adding missing of_node_put() PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put() tools: PCI: Exit with error code when test fails
| * PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put()Wen Yang2019-04-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to of_parse_phandle() returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pci/controller/dwc/pci-layerscape.c:204:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 198, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Minghuan Lian <minghuan.Lian@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Roy Zang <roy.zang@nxp.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org
| * PCI: uniphier: Fix a leaked reference by adding missing of_node_put()Wen Yang2019-03-291-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to of_get_child_by_name() returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. irq_domain_add_linear() also calls of_node_get() to increase refcount, so irq_domain will not be affected when it is released. Detected by coccinelle with the following warnings: ./drivers/pci/controller/dwc/pcie-uniphier.c:283:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 274, but without a corresponding object release within this function. ./drivers/pci/controller/dwc/pcie-uniphier.c:290:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 274, but without a corresponding object release within this function. ./drivers/pci/controller/dwc/pcie-uniphier.c:296:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 274, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org
| * PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put()Wen Yang2019-03-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to of_get_next_child() returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. irq_domain_add_linear() also calls of_node_get() to increase refcount, so irq_domain will not be affected when it is released. Detected by coccinelle with the following warnings: ./drivers/pci/controller/dwc/pci-dra7xx.c:252:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function. ./drivers/pci/controller/dwc/pci-dra7xx.c:255:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-omap@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org
* | Merge branch 'remotes/lorenzo/pci/keystone'Bjorn Helgaas2019-05-1410-353/+835
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move IRQ register address computation inside macros (Kishon Vijay Abraham I) - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I) - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham I) - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon Vijay Abraham I) - Add dwc support for platforms with custom MSI controllers (Kishon Vijay Abraham I) - Add keystone-specific MSI controller (Kishon Vijay Abraham I) - Remove dwc host_ops previously used for keystone-specific MSI (Kishon Vijay Abraham I) - Skip dwc default MSI init if platform has custom MSI controller (Kishon Vijay Abraham I) - Implement .start_link() and .stop_link() for keystone endpoint support (Kishon Vijay Abraham I) - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I) - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon Vijay Abraham I) - Get keystone register resources from DT by name, not index (Kishon Vijay Abraham I) - Get DT resources in .probe() to prepare for endpoint support (Kishon Vijay Abraham I) - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration (Kishon Vijay Abraham I) - Explicitly set keystone to host mode (Kishon Vijay Abraham I) - Document DT "atu" reg-names requirement for DesignWare core >= 4.80 (Kishon Vijay Abraham I) - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon Vijay Abraham I) - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon Vijay Abraham I) - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham I) - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham I) - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I) - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I) - Make of_pci_get_max_link_speed() available to endpoint drivers as well as host drivers (Kishon Vijay Abraham I) - Add keystone support for DT "max-link-speed" property (Kishon Vijay Abraham I) - Add endpoint library support for BAR buffer alignment (Kishon Vijay Abraham I) - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I) - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay Abraham I) - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon Vijay Abraham I) - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay Abraham I) - Configure designware endpoints to advertise smallest resizable BAR (1MB) (Kishon Vijay Abraham I) - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay Abraham I) - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I) - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test misc: pci_endpoint_test: Add support to test PCI EP in AM654x PCI: designware-ep: Use aligned ATU window for raising MSI interrupts PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size PCI: keystone: Add support for PCIe EP in AM654x Platforms dt-bindings: PCI: Add PCI EP DT binding documentation for AM654 PCI: dwc: Add callbacks for accessing dbi2 address space PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops PCI: endpoint: Add support to specify alignment for buffers allocated to BARs PCI: keystone: Add support to set the max link speed from DT PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers PCI: keystone: Invoke phy_reset() API before enabling PHY PCI: keystone: Add support for PCIe RC in AM654x Platforms dt-bindings: PCI: Add PCI RC DT binding documentation for AM654 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: dwc: Enable iATU unroll for endpoint too dt-bindings: PCI: Document "atu" reg-names PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Move resources initialization to prepare for EP support PCI: keystone: Use platform_get_resource_byname() to get memory resources PCI: keystone: Perform host initialization in a single function dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Cleanup error_irq configuration PCI: keystone: Add start_link()/stop_link() dw_pcie_ops PCI: dwc: Remove default MSI initialization for platform specific MSI chips PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Cleanup ks_pcie_msi_irq_handler() PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Cleanup interrupt related macros # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h
| * | PCI: designware-ep: Use aligned ATU window for raising MSI interruptsKishon Vijay Abraham I2019-05-011-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configure an aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest sizeKishon Vijay Abraham I2019-05-011-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the Resizable BAR capability to advertise the smallest size (1MB) for a couple of reasons: - Host side resource allocation of BAR fails for larger sizes - Endpoint function driver does not allocate memory for all supported sizes in the Resizable BAR capability. If and when there is a usecase required to add more flexibility using the Resizable BAR capability, this can be revisited. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Add support for PCIe EP in AM654x PlatformsKishon Vijay Abraham I2019-05-012-37/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe EP support for AM654x Platforms in pci-keystone.c Link: https://lore.kernel.org/linux-pci/20190325093947.32633-15-kishon@ti.com/ Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: made dev_vdbg() call a comment] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Add callbacks for accessing dbi2 address spaceKishon Vijay Abraham I2019-04-162-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain platforms like TI's AM654 do not have aseparate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offsetKishon Vijay Abraham I2019-04-161-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability() and __dw_pcie_ep_find_next_cap() for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present because of incorrect ordering of the "next_cap_ptr" check. Fix it. Fixes: beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Add const qualifier to struct dw_pcie_ep_opsKishon Vijay Abraham I2019-04-155-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Add support to set the max link speed from DTKishon Vijay Abraham I2019-04-151-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe does not work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" DT property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Invoke phy_reset() API before enabling PHYKishon Vijay Abraham I2019-04-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke the phy_reset() API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Add support for PCIe RC in AM654x PlatformsKishon Vijay Abraham I2019-04-152-15/+148
| | | | | | | | | | | | | | | | | | | | | Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64Kishon Vijay Abraham I2019-04-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hook_fault_code() is an ARM32 specific API for hooking into data abort. AM65X platforms (that integrate ARM v8 cores and select CONFIG_ARM64 as arch) rely on pci-keystone.c but on them the enumeration of a non-present BDF does not trigger a bus error, so the fixup exception provided by calling hook_fault_code() is not needed and can be guarded with CONFIG_ARM. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Fix ATU identification for designware version >= 4.80Kishon Vijay Abraham I2019-04-152-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which have not populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Enable iATU unroll for endpoint tooKishon Vijay Abraham I2019-04-153-23/+19Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup() which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Explicitly set the PCIe modeKishon Vijay Abraham I2019-04-151-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Move resources initialization to prepare for EP supportKishon Vijay Abraham I2019-04-151-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move platform_get_resource() calls for resources that are applicable to both host and endpoint mode (ie "dbics" and "app") from ks_add_pcie_port() to the probe() callback, in preparation for adding endpoint support to pci-keystone driver. No functional change intended. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Use platform_get_resource_byname() to get memory resourcesKishon Vijay Abraham I2019-04-111-10/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use platform_get_resource_byname() instead of platform_get_resource() which uses an index to get memory resources. While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since the pci-keystone driver has never worked in the mainline kernel, DT backward compatibility is not an issue. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Perform host initialization in a single functionKishon Vijay Abraham I2019-04-111-40/+23Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change. Instead of having two functions ks_pcie_add_pcie_port() and ks_pcie_dw_host_init() for initializing host, have a single function to perform all the host initialization. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Cleanup error_irq configurationKishon Vijay Abraham I2019-04-111-26/+17Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci-keystone driver uses irq_of_parse_and_map() to get irq number of error_irq. Use platform_get_irq() instead and move platform_get_irq() and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe since error_irq is common to both RC mode and EP mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Add start_link()/stop_link() dw_pcie_opsKishon Vijay Abraham I2019-04-111-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add start_link()/stop_link() dw_pcie_ops and invoke ks_pcie_start_link() directly from host_init. start_link()/stop_link() ops are required for adding EP mode support. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Remove default MSI initialization for platform specific MSI chipsKishon Vijay Abraham I2019-04-041-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms which populate msi_host_init() have their own MSI controller logic. Writing to MSI control registers on platforms which do not use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses its own MSI controller logic instead of Designware's MSI one. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Remove Keystone specific dw_pcie_host_opsKishon Vijay Abraham I2019-04-042-41/+14Star
| | | | | | | | | | | | | | | | | | | | | | | | Now that Keystone started using its own msi_irq_chip, remove Keystone specific callback functions defined in dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Use Keystone specific msi_irq_chipKishon Vijay Abraham I2019-04-042-27/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use Keystone specific msi_irq_chip to configure the MSI controller logic in the PCIe keystone wrapper instead of using the default Designware msi_irq chip (dw_pci_msi_bottom_irq_chip) with callback functions for configuring the Keystone MSI controller. This will help to remove Keystone specific callback functions added in dw_pcie_host_ops. Move the default msi_irq_chip assignment to dw_pcie_host_init since platforms that doesn't use the default msi_irq_chip will assign msi_irq_chip in the msi_host_init() callback. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: dwc: Add support to use non default msi_irq_chipKishon Vijay Abraham I2019-04-042-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms using DesignWare IP use dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the DesignWare IP. However certain platforms like Keystone (K2G) which uses DesignWare IP have their own MSI controller logic. For handling such platforms, the irqchip ops use msi_irq_ack(), msi_set_irq(), msi_clear_irq() callback functions. Add support to use different msi_irq_chip with default set to dw_pci_msi_bottom_irq_chip. This is in preparation to get rid of msi_irq_ack(), msi_set_irq(), msi_clear_irq() and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Cleanup ks_pcie_msi_irq_handler()Kishon Vijay Abraham I2019-04-041-36/+28Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ks_pcie_msi_irq_handler() invokes ks_pcie_handle_msi_irq() for handling the interrupts. Having two functions for handling the interrupt was used when keystone PCIe driver was implemented using two files but with commit b492aca35c98 ("PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c"), which merged the keystone PCIe driver to use a single file, two functions for handling the interrupt handler are not required. Handle MSI interrupt in a single interrupt handler here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Use hwirq to get the MSI IRQ number offsetKishon Vijay Abraham I2019-04-041-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ks_pcie_msi_irq_handler() uses 'virq' to get the IRQ number offset. This offset is used to get the correct MSI_IRQ_STATUS register corresponding to the IRQ line that raised the interrupt. There is no guarantee that 'virq' assigned for consecutive hardware IRQ will be contiguous and this might get us an incorrect IRQ number offset. Fix it here by using 'hwirq' to get the IRQ number offset. Since we don't store the 'virq' numbers of all the IRQ numbers, stop checking if irq count is greater than MAX_MSI_HOST_IRQS and remove MAX_MSI_HOST_IRQS. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Add separate functions for configuring MSI and legacy interruptKishon Vijay Abraham I2019-04-041-92/+89Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ks_pcie_get_irq_controller_info() is used to configure both MSI and legacy interrupt. This will prevent MSI or legacy interrupt specific intializations. Add separate functions to configure MSI and legacy interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| * | PCI: keystone: Cleanup interrupt related macrosKishon Vijay Abraham I2019-04-041-13/+13
| |/ | | | | | | | | | | | | | | | | No functional change. Change both MSI interrupt and legacy interrupt related macros to take an additional argument in order to return the correct register offset. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
* | Merge branch 'remotes/lorenzo/pci/imx'Bjorn Helgaas2019-05-143-96/+62Star
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Simplify imx7d_pcie_wait_for_phy_pll_lock() by using regmap_read_poll_timeout() (Andrey Smirnov) - Drop imx6_pcie_wait_for_link() in favor of the more generic dw_pcie_wait_for_link() (Andrey Smirnov) - Return -ETIMEDOUT instead of -EINVAL from imx6_pcie_wait_for_speed_change() (Andrey Smirnov) - Remove unused PCIE_PL_PFLR_* constants from imx6 (Andrey Smirnov) - Use shared PHY debug register definitions in imx6 (Andrey Smirnov) - Use BIT() in imx6 (Andrey Smirnov) - Simplify imx6 PHY bit operations (Andrey Smirnov) - Simplify imx6 pcie_phy_poll_ack() (Andrey Smirnov) - Use data types that match actual imx6 PHY register width (Andrey Smirnov) - Mark imx6 suspend support with drvdata flags instead of checking variants (Andrey Smirnov) - Sleep instead of delay in imx6_pcie_enable_ref_clk() (Andrey Smirnov) * remotes/lorenzo/pci/imx: PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk() PCI: imx6: Use flags to indicate support for suspend PCI: imx6: Restrict PHY register data to 16-bit PCI: imx6: Simplify pcie_phy_poll_ack() PCI: imx6: Simplify bit operations in PHY functions PCI: imx6: Make use of BIT() in constant definitions PCI: dwc: imx6: Share PHY debug register definitions PCI: imx6: Remove PCIE_PL_PFLR_* constants PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change() PCI: imx6: Drop imx6_pcie_wait_for_link() PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()
| * | PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()Andrey Smirnov2019-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | imx6_pcie_enable_ref_clk() is never called in atomic context, so there's no need to use udelay(). Replace it with usleep_range(). Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| * | PCI: imx6: Use flags to indicate support for suspendAndrey Smirnov2019-05-011-9/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that driver data has flags variable that can be used to indicate quirks/features supported we can switch the code to use it instead of having a special function that does so based on variant alone. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| * | PCI: imx6: Restrict PHY register data to 16-bitAndrey Smirnov2019-05-011-7/+6Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PHY registers on i.MX6 are 16-bit wide, so we can get rid of explicit masking if we restrict pcie_phy_read()/pcie_phy_write() to use 'u16' instead of 'int'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| * | PCI: imx6: Simplify pcie_phy_poll_ack()Andrey Smirnov2019-05-011-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify pcie_phy_poll_ack() by incorporating shifting into constant definition and convert the code to use 'bool'. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
| * | PCI: imx6: Simplify bit operations in PHY functionsAndrey Smirnov2019-05-011-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the code by incorporating left shifts into constant definitions as well as using FIELD_PREP/GENMASK. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-05-07 15:56:48 +0200