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This commit adds a pinctrl driver for the CP110 part of the Marvell
Armada 7K and 8K SoCs. The Armada 7K has a single CP110, where almost all
the MPP pins are available. On the other side, the Armada 8K has two
CP110, and the available MPPs are split between the master CP110 (MPPs 32
to 62) and the slave CP110 (MPPs 0 to 31).
The register interface to control the MPPs is however the same as all
other mvebu SoCs, so we can reuse the common pinctrl-mvebu.c logic.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl and 4.9 changes:
- converted to simple_mmio
- converted to syscon/regmap
- removed unimplemented .remove function
- dropped DTS changes
- defered gpio ranges to DT
- fixed warning
- properly set soc->nmodes
-- rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
[ add missing MPP[61:56] function 14 (SDIO)
-- Konstantin Porotchkin]
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[ allow to properly register more then one instance of this driver
-- Grzegorz Jaszczyk]
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
[ - rebased on 4.12-rc1
- fixed the 80 character limit for mvebu_mpp_mode array
- aligned the compatible name on the ones already used
- fixed the MPP table for CP110: some MPP are not available on Armada 7K
-- Gregory CLEMENT]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This commit adds a pinctrl driver for the pin-muxing controller found in
the AP806 part of the Marvell Armada 7K and 8K SoCs. Its register
interface is compatible with the one used by previous mvebu pin
controllers, so the common logic in drivers/pinctrl/mvebu/pinctrl-mvebu.c
is used.
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Shadi Ammouri <shadi@marvell.com>
[updated for mvebu pinctrl changes
- converted to simple_mmio
- removed unimplemented .remove function
- removed DTS description
- converted to use syscon/regmap
--rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The Armada 37xx SoC come with 2 pin controllers: one on the south
bridge (managing 28 pins) and one on the north bridge (managing 36 pins).
At the hardware level the controller configure the pins by group and not
pin by pin. This constraint is reflected in the design of the driver:
only the group related functions are implemented.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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CONFIG_PINCTRL_MVEBU is more suitable than CONFIG_PLAT_ORION
to guard the drivers/pinctrl/mvebu/ directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
support pin-muxing on Marvell EBU processors. Two variants of the
Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada
398), which have a few differences in the available functions for
certain pins.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Like the spear platform, the mvebu platform has multiple files: one
core file, and then one file per SoC family. More files will be added
later, as support for mach-orion5x and mach-mv78xx0 SoCs is added to
pinctrl-mvebu. For those reasons, having a separate subdirectory,
drivers/pinctrl/mvebu/ makes sense, and it had already been suggested
by Linus Wallej when the driver was originally submitted.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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