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* Merge tag 'pwm/for-4.13-rc1' of ↵Linus Torvalds2017-07-137-132/+211
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This release cycle's changes include mostly updates and cleanups to existing drivers along with a few cleanups to the core, documentation and device tree bindings" * tag 'pwm/for-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: cros-ec: Fix transposed param settings pwm: meson: Improve PWM calculation precision dt-bindings: pwm: meson: Add compatible for gxbb ao PWMs pwm: meson: Add compatible for the gxbb ao PWMs pwm: sun4i: Drop legacy callbacks pwm: sun4i: Switch to atomic PWM pwm: sun4i: Improve hardware read out pwm: hibvt: Constify hibvt_pwm_ops pwm: Silently error out on EPROBE_DEFER pwm: Standardize document format pwm: bfin: Remove unneeded error message dt-bindings: pwm: Update STM32 timers clock names dt-bindings: pwm: Add R-Car M3-W device tree bindings pwm: tegra: Set maximum pwm clock source per SoC tapeout
| * Merge branch 'for-4.13/drivers' into for-nextThierry Reding2017-07-066-131/+208
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| | * pwm: cros-ec: Fix transposed param settingsNick Vaccaro2017-07-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __cros_ec_pwm_get_duty() routine was transposing the insize and outsize fields when calling cros_ec_cmd_xfer_status(). The original code worked without error due to size of the two particular parameter blocks passed to cros_ec_cmd_xfer_status(), so this change is not fixing an actual runtime problem, just correcting the calling usage. Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: meson: Improve PWM calculation precisionJerome Brunet2017-07-061-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using input clocks with high rates, such as clk81 (166MHz), the fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error. Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000 fin_ns = 5,9999999 which is, of course, rounded down to 5. This introduces an error of ~20% on the period requested from the PWM. This patch uses ps instead of ns (and 64 bit integers) to perform the calculation. This should give a good enough precision. Fixes: 211ed630753d ("pwm: Add support for Meson PWM Controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> squash! pwm: meson: Improve pwm calculation precision
| | * pwm: meson: Add compatible for the gxbb ao PWMsJerome Brunet2017-07-061-3/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the gxbb (and gxl) family, the PWMs of the AO domain require a specific compatible because the possible input clocks are different from the EE PWMs input clocks. Since the number of possible input clocks is also different, the 'num_parents' field is added to all the Meson PWM data. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: sun4i: Drop legacy callbacksAlexandre Belloni2017-07-061-160/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the legacy callbacks .enable(), .disable(), .set_polarity() and .config(). Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: sun4i: Switch to atomic PWMAlexandre Belloni2017-07-061-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the driver to atomic PWM. This makes it easier to wait a proper amount of time when changing the duty cycle before disabling the channel (main use case is switching the duty cycle to 0 before disabling). Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: sun4i: Improve hardware read outAlexandre Belloni2017-07-061-19/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement .get_state instead of only reading the polarity at probe time. This allows to get the proper state, period and duty cycle. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: hibvt: Constify hibvt_pwm_opsArvind Yadav2017-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | File size before: text data bss dec hex filename 1510 296 0 1806 70e drivers/pwm/pwm-hibvt.o File size After adding 'const': text data bss dec hex filename 1606 192 0 1798 706 drivers/pwm/pwm-hibvt.o Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: bfin: Remove unneeded error messageMarkus Elfring2017-07-061-3/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdf Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: tegra: Set maximum pwm clock source per SoC tapeoutLaxman Dewangan2017-06-131-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PWM hardware IP is taped-out with different maximum frequency on different SoCs. From HW team: Before Tegra186, it is 48 MHz. In Tegra186, it is 102 MHz. Add support to limit the clock source frequency to the maximum IP supported frequency. Provide these values via SoC chipdata. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * | pwm: Silently error out on EPROBE_DEFERJerome Brunet2017-07-061-1/+3
| |/ | | | | | | | | | | | | | | | | In of_pwm_get(), if we fail to get the PWM chip due to probe deferal, we shouldn't print an error message. Just be silent in this case. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* / pwm: jz4740: Let the pinctrl driver configure the pinsPaul Cercueil2017-05-221-29/+0Star
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on the pins being properly configured before the driver probes. One inherent problem of this new approach is that the pinctrl framework does not allow us to configure each pin on demand, when the various PWM channels are requested or released. For instance, the PWM channels can be configured from sysfs, which would require all PWM pins to be configured properly beforehand for the PWM function, eventually causing conflicts with other platform or board drivers. The proper solution here would be to modify the pwm-jz4740 driver to handle only one PWM channel, and create an instance of this driver for each one of the 8 PWM channels. Then, it could use the pinctrl framework to dynamically configure the PWM pin it controls. Until this can be done, the only jz4740 board supported upstream (Qi lb60) can configure all of its connected PWM pins in PWM function mode, since those are not used by other drivers nor by GPIOs on the board. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'for-4.12/drivers' into for-nextThierry Reding2017-04-137-309/+605
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| * pwm: tegra: Read PWM clock source rate in driver initLaxman Dewangan2017-04-131-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is required to know the PWM clock source frequency to calculate the PWM period. In driver, the clock source frequency of the PWM does not get change and, hence, get the clock source frequency in driver init. Get this values later for period calculation from pwm_config(). This will help in avoiding the clock call for getting clock rate in the pwm_config() each time. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: pca9685: Fix GPIO-only operationSven Van Asbroeck2017-04-131-33/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO-only driver operation never clears the SLEEP bit, which can cause the GPIOs to become unusable. Example: 1. user requests first PWM -> driver clears SLEEP bit 2. user frees last PWM -> driver sets SLEEP bit 3. user requests GPIO 4. user switches GPIO on -> output does not turn on because SLEEP bit is set Prevent this behaviour by letting the runtime PM framework control the SLEEP bit. This will put the chip to SLEEP if no PWMs/GPIOs are exported or in use. Fixes: bccec89f0a35 ("Allow any of the 16 PWMs to be used as a GPIO") Reported-by: Sven Van Asbroeck <TheSven73@googlemail.com> Signed-off-by: Sven Van Asbroeck <TheSven73@googlemail.com> Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: mediatek: Don't explicitly set .ownerkbuild test robot2017-04-131-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | drivers/pwm/pwm-mediatek.c:210:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci CC: John Crispin <john@phrozen.org> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Avoid potential overflow for short periodsThierry Reding2017-04-131-6/+4Star
| | | | | | | | | | | | | | | | | | | | For very short periods, the result of the division might overflow the unsigned long hz variable (on 32-bit architectures). Avoid that by making it an unsigned long long. While at it, also remove an unneeded local variable whose only purpose is to store a temporary computation. Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Add support to configure pin state in suspends/resumeLaxman Dewangan2017-04-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some of NVIDIA Tegra's platform, PWM controller is used to control the PWM controlled regulators. PWM signal is connected to the VID pin of the regulator where duty cycle of PWM signal decide the voltage level of the regulator output. When system enters suspend, some PWM client/slave regulator devices require the PWM output to be tristated. Add support to configure the pin state via pinctrl frameworks in suspend and active state of the system. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Increase precision in PWM rate calculationLaxman Dewangan2017-04-121-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rate of the PWM calculated as follows: hz = NSEC_PER_SEC / period_ns; rate = (rate + (hz / 2)) / hz; This has the precision loss in lower PWM rate. Change this to have more precision as: hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns); rate = DIV_ROUND_CLOSEST(rate * 100, hz) Example: 1. period_ns = 16672000, PWM clock rate is 200 KHz. Based on old formula hz = NSEC_PER_SEC / period_ns = 1000000000ul/16672000 = 59 (59.98) rate = (200K + 59/2)/59 = 3390 Based on new method: hz = 5998 rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334 If we measure the PWM signal rate, we will get more accurate period with rate value of 3334 instead of 3390. 2. period_ns = 16803898, PWM clock rate is 200 KHz. Based on old formula: hz = 59, rate = 3390 Based on new formula: hz = 5951, rate = 3360 The PWM signal rate of 3360 is more near to requested period than 3333. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local implementationLaxman Dewangan2017-04-121-2/+1Star
| | | | | | | | | | | | | | | | Use macro DIV_ROUND_CLOSEST_ULL() for 64-bit division to closest one instead of implementing the same locally. This increase readability. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: Add MediaTek PWM supportJohn Crispin2017-04-063-0/+230
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the PWM core found on current ARM base SoCs made by MediaTek. This IP core supports 5 channels and has 2 operational modes. There is the old mode, which is a classical PWM and the new mode which allows the user to define bitmasks that get clocked out on the pins. As the subsystem currently only supports PWM cores with the "old" mode, we can safely ignore the "new" mode for now. Signed-off-by: John Crispin <john@phrozen.org> [thierry.reding@gmail.com: minor cleanups] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: atmel: Enable PWM on sama5d2Claudiu Beznea2017-04-061-0/+3
| | | | | | | | | | | | | | | | | | sama5d2 can use the same atmel_pwm_data as sama5d3. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: atmel: Switch to atomic PWMClaudiu Beznea2017-04-061-144/+129Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The currently Atmel PWM controllers supported by this driver could change period or duty factor without channel disable, for regular channels (sama5d3 support this by using period or duty factor update registers, sam9rl support this by writing channel update register and select the corresponding update: period or duty factor). The chip doesn't support run time changings of signal polarity. To take advantage of atomic PWM framework and let controller works without glitches, in this patch only the duty factor could be changed without disabling PWM channel. For period and signal polarity the atomic PWM is simulated by disabling + enabling the right PWM channel. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: atmel-hlcdc: Implement the suspend/resume hooksBoris Brezillon2017-04-061-0/+35
| | | | | | | | | | | | | | | | Implement the suspend/resume hooks to make sure the PWM device is restored to a correct state after a suspend. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * pwm: atmel-hlcdc: Convert to the atomic PWM APIBoris Brezillon2017-04-061-126/+101Star
| | | | | | | | | | | | | | | | | | Implement the ->apply() hook and drop the ->enable(), ->disable, ->set_polarity and ->config() ones. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* | pwm: rockchip: State of PWM clock should synchronize with PWM enabled stateDavid Wu2017-04-061-7/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the PWM was not enabled at U-Boot loader, PWM could not work for clock always disabled at PWM driver. The PWM clock is enabled at beginning of pwm_apply(), but disabled at end of pwm_apply(). If the PWM was enabled at U-Boot loader, PWM clock is always enabled unless closed by ATF. The pwm-backlight might turn off the power at early suspend, should disable PWM clock for saving power consume. It is important to provide opportunity to enable/disable clock at PWM driver, the PWM consumer should ensure correct order to call PWM enable and disable, and PWM driver ensure state of PWM clock synchronized with PWM enabled state. Fixes: 2bf1c98aa5a4 ("pwm: rockchip: Add support for atomic update") Cc: stable@vger.kernel.org Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* | pwm: lpss: Set enable-bit before waiting for update-bit to go lowHans de Goede2017-04-064-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least on cherrytrail, the update bit will never go low when the enabled bit is not set. This causes the backlight on my cube iwork8 air tablet to never turn on again after being turned off because in the pwm_lpss_apply enable path pwm_lpss_update will fail causing an error exit and the enable-bit to never get set. Any following pwm_lpss_apply calls will fail the pwm_lpss_is_updating check. Since the docs say that the update bit should be set before the enable-bit, split pwm_lpss_update into setting the update-bit and pwm_lpss_wait_for_update, and move the pwm_lpss_wait_for_update call in the enable path to after setting the enable-bit. Fixes: 10d56a4 ("pwm: lpss: Avoid reconfiguring while UPDATE bit...") Cc: Ilkka Koskinen <ilkka.koskinen@intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* | pwm: lpss: Split Tangier configurationAndy Shevchenko2017-04-061-1/+8
|/ | | | | | | | | | As a preparation for special treatment for Broxton we split Tangier configuration. Fixes: b89b4b7a3d0a ("pwm: lpss: pci: Enable PWM module on Intel Edison") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
* Merge tag 'pwm/for-4.11-rc1' of ↵Linus Torvalds2017-03-0123-275/+445
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This set contains mostly fixes to existing drivers as well as cleanup of code that's not been in active use for a while" * tag 'pwm/for-4.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (27 commits) acpi: lpss: call pwm_add_table() for BSW PWM device pwm: Try to load modules during pwm_get() pwm: Don't hold pwm_lookup_lock longer than necessary pwm: Make the PWM_POLARITY flag in DTB optional pwm: Print error messages with pr_err() instead of pr_debug() pwm: imx: Add polarity inversion support to i.MX's PWMv2 pwm: imx: doc: Update imx-pwm.txt documentation entry pwm: imx: Remove redundant i.MX PWMv2 code pwm: imx: Provide atomic PWM support for i.MX PWMv2 pwm: imx: Move PWMv2 wait for fifo slot code to a separate function pwm: imx: Move PWMv2 software reset code to a separate function pwm: imx: Rewrite v1 code to facilitate switch to atomic PWM pwm: imx: Add separate set of PWM ops for v1 and v2 pwm: imx: Remove ipg clock and enable per clock when required pwm: lpss: Add Intel Gemini Lake PCI ID pwm: lpss: Do not export board infos for different PWM types pwm: lpss: Avoid reconfiguring while UPDATE bit is still enabled pwm: lpss: Switch to new atomic API pwm: lpss: Allow duty cycle to be 0 pwm: lpss: Avoid potential overflow of base_unit ...
| * Merge branch 'for-4.11/drivers' into for-nextThierry Reding2017-02-1010-227/+408
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| | * pwm: imx: Add polarity inversion support to i.MX's PWMv2Lukasz Majewski2017-01-301-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch the polarity settings for i.MX's PWMv2 is now supported on top of atomic PWM setting Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Remove redundant i.MX PWMv2 codeLukasz Majewski2017-01-301-127/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code providing functionality surpassed by the atomic PWM is not needed anymore and hence can be removed. Suggested-by: Stefan Agner <stefan@agner.ch> Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Provide atomic PWM support for i.MX PWMv2Lukasz Majewski2017-01-301-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit provides apply() callback implementation for i.MX's PWMv2. Suggested-by: Stefan Agner <stefan@agner.ch> Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Move PWMv2 wait for fifo slot code to a separate functionLukasz Majewski2017-01-301-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code, which waits for fifo slot, has been extracted from imx_pwm_config_v2 function and moved to new one - imx_pwm_wait_fifo_slot(). This change reduces the overall size of imx_pwm_config_v2() and prepares it for atomic PWM operation. Suggested-by: Stefan Agner <stefan@agner.ch> Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Move PWMv2 software reset code to a separate functionLukasz Majewski2017-01-301-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The software reset code has been extracted from imx_pwm_config_v2 function and moved to new one - imx_pwm_sw_reset(). This change reduces the overall size of imx_pwm_config_v2() and prepares it for atomic PWM operation. Suggested-by: Stefan Agner <stefan@agner.ch> Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Rewrite v1 code to facilitate switch to atomic PWMLukasz Majewski2017-01-301-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code has been rewritten to remove "generic" calls to imx_pwm_{enable|disable|config}. Such approach would facilitate switch to atomic PWM (a.k.a ->apply()) implementation. Suggested-by: Stefan Agner <stefan@agner.ch> Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Add separate set of PWM ops for v1 and v2Lukasz Majewski2017-01-301-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides separate set of PWM operations utilized by i.MX's v1 and v2 of the PWM hardware. Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Lukasz Majewski <l.majewski@majess.pl> Acked-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: imx: Remove ipg clock and enable per clock when requiredSascha Hauer2017-01-301-10/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The use of the ipg clock was introduced with commit 7b27c160c681 ("pwm: i.MX: fix clock lookup"). In the commit message it was claimed that the ipg clock is enabled for register accesses. This is true for the ->config() callback, but not for the ->set_enable() callback. Given that the ipg clock is not consistently enabled for all register accesses we can assume that either it is not required at all or that the current code does not work. Remove the ipg clock code for now so that it's no longer in the way of refactoring the driver. On the other hand, the i.MX 7 IP requires the peripheral clock to be enabled before accessing its registers. Since ->config() can be called when the PWM is disabled (in which case, the peripheral clock is also disabled), we need to surround the imx->config() with clk_prepare_enable(per_clk)/clk_disable_unprepare(per_clk) calls. Note that the driver was working fine for the i.MX 7 IP so far because the ipg and peripheral clock use the same hardware clock gate, which guaranteed peripheral clock activation even when ->config() was called when the PWM was disabled. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: lpss: Add Intel Gemini Lake PCI IDMika Westerberg2017-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Gemini Lake PWM is pretty much same as used in Intel Broxton. Add this new PCI ID to the list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: lpss: Do not export board infos for different PWM typesAndy Shevchenko2017-01-304-28/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PWM LPSS probe drivers just pass a pointer to the exported board info structures to pwm_lpss_probe() based on device PCI or ACPI ID. In order to remove the knowledge of specific devices from library part of the driver and reduce noise in exported namespace just duplicate the board info structures and stop exporting them. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: lpss: Avoid reconfiguring while UPDATE bit is still enabledIlkka Koskinen2017-01-301-9/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PWM Configuration register has SW_UPDATE bit that is set when a new configuration is written to the register. The bit is automatically cleared at the start of the next output cycle by the IP block. If one writes a new configuration to the register while it still has the bit enabled, PWM may freeze. That is, while one can still write to the register, it won't have an effect. Thus, we try to sleep long enough that the bit gets cleared and make sure the bit is not enabled while we update the configuration. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Richard Griffiths <richard.a.griffiths@intel.com> Signed-off-by: Ilkka Koskinen <ilkka.koskinen@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: lpss: Switch to new atomic APIAndy Shevchenko2017-01-301-35/+29Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of doing things separately, which is not so reliable on some platforms, switch the driver to use new atomic API, i.e. ->apply() callback. The change has been tested on Intel platforms such as Broxton, BayTrail, and Merrifield. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: lpss: Allow duty cycle to be 0Andy Shevchenko2017-01-301-2/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A duty cycle is represented by values [0..<period>] which reflects [0%..100%]. 0% of the duty cycle means always off (logical "0") on output. Allow this in the driver. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: lpss: Avoid potential overflow of base_unitAndy Shevchenko2017-01-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The resolution of base_unit is derived from base_unit_bits and thus must be equal to (2^base_unit_bits - 1). Otherwise frequency and therefore base_unit might potentially overflow. Prevent the above by substracting 1 in all cases where base_unit_bits or derivative is used. Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: pca9685: Fix period change with same duty cycleClemens Gruber2017-01-201-11/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When first implementing support for changing the output frequency, an optimization was added to continue the PWM after changing the prescaler without having to reprogram the ON and OFF registers for the duty cycle, in case the duty cycle stayed the same. This was flawed, because we compared the absolute value of the duty cycle in nanoseconds instead of the ratio to the period. Fix the problem by removing the shortcut. Fixes: 01ec8472009c9 ("pwm-pca9685: Support changing the output frequency") Cc: <stable@vger.kernel.org> # v4.3+ Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: constify pwm_ops structuresBhumika Goyal2017-01-194-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Declare pwm_ops structures as const as they are only stored in the ops field of a pwm_chip structure. This field is of type const struct pwm_ops *, so pwm_ops structures having this property can be declared as const. Done using Coccinelle: @r1 disable optional_qualifier@ identifier i; position p; @@ static struct pwm_ops i@p={...}; @ok1@ identifier r1.i; position p; struct pxa_pwm_chip pwm; struct bfin_pwm_chip bwm; struct vt8500_chip vp; struct imx_chip icp; @@ ( pwm.chip.ops=&i@p | bwm.chip.ops=&i@p | vp.chip.ops=&i@p | icp.chip.ops=&i@p ) @bad@ position p!={r1.p,ok1.p}; identifier r1.i; @@ i@p @depends on !bad disable optional_qualifier@ identifier r1.i; @@ +const struct pwm_ops i; File size details: text data bss dec hex filename 1646 328 0 1974 7b6 drivers/pwm/pwm-imx.o 1742 224 0 1966 7ae drivers/pwm/pwm-imx.o 1941 296 0 2237 8bd drivers/pwm/pwm-pxa.o 2037 192 0 2229 8b5 drivers/pwm/pwm-pxa.o 1946 296 0 2242 8c2 drivers/pwm/pwm-vt8500.o 2050 192 0 2242 8c2 drivers/pwm/pwm-vt8500.o The drivers/pwm/pwm-bfin.o file did not compile. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: bcm-iproc: Update dependencies for compile-testScott Branden2017-01-191-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dependency on COMMON_CLK and allow COMPILE_TEST for broader compile coverage. Default to Y for IPROC SoCs. This allows the driver to simply be enabled by selecting PWM. Signed-off-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> [thierry.reding@gmail.com: reword commit message] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| | * pwm: pca9685: Allow any of the 16 PWMs to be used as a GPIOMika Westerberg2017-01-191-1/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCA9685 controller has full on/off bit for each PWM channel. Setting this bit bypasses the PWM control and the line works just as it would be a GPIO. Furthermore in Intel Galileo it is actually used as GPIO output for discreet muxes on the board. This patch adds GPIO output only support for the driver so that we can control the muxes on Galileo using standard GPIO interfaces available in the kernel. GPIO and PWM functionality is exclusive so only one can be active at a time on a single PWM channel. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
| * | pwm: Try to load modules during pwm_get()Hans de Goede2017-01-301-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a module name string to the pwm_lookup struct and if specified try to load the module using request_module() if pwmchip_find_by_name() is unable to find the PWM chip. This is a last resort to work around drivers that can't - and can't be made to - deal with deferred probe. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [thierry.reding@gmail.com: rename new macro, reword commit message] [thierry.reding@gmail.com: add comment explaining use-case] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-04 06:11:53 +0200