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*---. Merge remote-tracking branches 'spi/topic/sirf', 'spi/topic/spidev' and ↵Mark Brown2015-06-185-261/+1778
|\ \ \ | | | | | | | | | | | | 'spi/topic/zynq' into spi-next
| | | * spi: zynq: Remove execute bitMark Brown2015-06-171-0/+0
| | | | | | | | | | | | | | | | Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * spi: Add support for Zynq Ultrascale+ MPSoC GQSPI controllerRanjit Waghmode2015-06-123-0/+1129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for GQSPI controller driver used by Zynq Ultrascale+ MPSoC Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | spi: spidev: Remove unneeded variableFabio Estevam2015-05-111-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unneeded variable used to store return value. The semantic patch that makes this change is available in scripts/coccinelle/misc/returnvar.cocci. More information about semantic patching is available at http://coccinelle.lip6.fr/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | spi: spidev: use spi_sync instead of spi_asyncMartin Sperl2015-04-231-21/+9Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has the benefit that the "optimization" of the framework in regards to spi_sync will also benefit spidev users directly and allow running spi transfers without a necessary context-switch to message-pump. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: sirf: add the reset for USP-based SPIQipan Li2015-05-261-28/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USP-based SPI need a disable and enable, otherwise it doesn't work. this patch adds it as HW initialization. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: sirf: remove the allocation of dummypageQipan Li2015-05-261-9/+3Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this job has been done by spi core. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: sirf: add support for USP-based SPIQipan Li2015-05-201-208/+584
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USP is a general purpose serial port in SiRFSoC, which can work as SPI. the most data flow of USP and pure SPI is same with main differences in registers layout. this patch moves registers layout to private data, and use flags to differentiate other minor differences between prima2-spi, prima2-usp and atlas7-usp for hardware configuration. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: sirf: replace kmalloc by devm_kzallocQipan Li2015-05-071-5/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: sirf: request and free cs gpio in setup and cleanup callbacksQipan Li2015-05-061-18/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | move spi controller's gpio request work out from probe() to spi device register stage, so after spi device register spi controller can deactive device's gpio chipselect. old code can't do it because gpio request has not be done until device register is finised in spi_bitbang_start. and add cleanup function to free CS gpio. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: sirf: replace BUG condition by error code for unsupported transferQipan Li2015-04-271-1/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | return error for unsupported bits-per-word format, BUG() is not right for this scenerios as we are not an ASSERT but an error handler. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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*-------. \ \ Merge remote-tracking branches 'spi/topic/pxa', 'spi/topic/rb4xx', ↵Mark Brown2015-06-1810-586/+328Star
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | 'spi/topic/rspi', 'spi/topic/s3c64xx' and 'spi/topic/sh-msiof' into spi-next
| | | | | * | | spi: sh-msiof: Constify platform_device_idKrzysztof Kozlowski2015-05-011-1/+1
| | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform_device_id is not modified by the driver and core uses it as const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | | * / / spi: s3c64xx: Constify platform_device_idKrzysztof Kozlowski2015-05-011-1/+1
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform_device_id is not modified by the driver and core uses it as const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * | | spi: rspi: Re-do the returning value of qspi_transfer_out_inHiep Cao Minh2015-06-021-5/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reduce complexity of code, drop "ret" then qspi_transfer_out_in function should return the value of "qspi_trigger_transfer_out_in" directly. Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * | | spi: rspi: modify the name of "qspi_trigger_transfer_out_int" functionHiep Cao Minh2015-06-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The name of "qspi_trigger_transfer_out_int" function should be "qspi_trigger_transfer_out_in" without "t". Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * | | spi: rspi: Re-do the returning value of rspi_dma_check_then_transferHiep Cao Minh2015-05-071-8/+5Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reduce indentation and complexity of code, insteeds of returning zero the function rspi_dma_check_then_transfer should return rspi_dma_transfer directly after checking error. Signed-off-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * | | spi: rspi: Constify platform_device_idKrzysztof Kozlowski2015-05-011-1/+1
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform_device_id is not modified by the driver and core uses it as const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | | spi: rb4xx: Fix checking return value of devm_ioremap_resource()Axel Lin2015-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_ioremap_resource() returns ERR_PTR on failure. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | | spi: rb4xx: Fix set_cs logic.Bert Vermeulen2015-04-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As it turns out, the set_cs() enable parameter refers to the logic level on the CS pin, not the state of chip selection. This broke functionality of the LEDs behind the CPLD, or at least delayed the commands until another one came in to toggle CS. Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | | spi: Add SPI driver for Mikrotik RB4xx series boardsBert Vermeulen2015-04-183-0/+217
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver mediates access between the connected CPLD and other devices on the bus. The m25p80-compatible boot flash and (some models) MMC use regular SPI, bitbanged as required by the SoC. However the SPI-connected CPLD has a two-wire mode, in which two bits are transferred per SPI clock cycle. The second bit is transmitted with the SoC's CS2 pin. Signed-off-by: Bert Vermeulen <bert@biot.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: pxa2xx: Constify ACPI device idsMathias Krause2015-06-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Constify the ACPI device ID array, it doesn't need to be writable at runtime. Signed-off-by: Mathias Krause <minipli@googlemail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: spi-pxa2xx: remove legacy PXA DMA bitsDaniel Mack2015-06-094-501/+2Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic DMA support was already implemented by commit cd7bed003404 ("spi/pxa2xx: break out the private DMA API usage into a separate file") which moved all the legacy PXA DMA implementation code into its own file. With generic DMA available for PXA, we can now just trash this file. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Mark Brown <broonie@linaro.org> [respin after pxa dmaengine support upstream] Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: pxa2xx: Make LPSS SPI general register optionalJarkko Nikula2015-06-051-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General register located in LPSS SPI private register space is not found in upcoming Intel LPSS platforms. Access it conditionally depending is it defined in configuration. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: pxa2xx: Prepare for new Intel LPSS SPI typeJarkko Nikula2015-06-051-48/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the Intel LPSS SPI properties will be different in upcoming platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI private registers will be at different offset and there will be changes in individual registers and default FIFO thresholds too. Add configuration for these differences and use them in runtime based on LPSS SSP type. With this change private registers offset autodetection becomes needless. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | spi: pxa2xx: Differentiate Intel LPSS typesJarkko Nikula2015-06-052-18/+34
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel LPSS SPI properties differ between between platforms. Now private registers offset 0x400 or 0x800 is autodetected but there is need to support also other offset and handle a few other differences. Prepare for that by splitting the LPSS_SSP type into compatible hardware types and set it now based on PCI or ACPI ID. That type will be used to set properties that differ between current and upcoming platforms. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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*-----. \ \ Merge remote-tracking branches 'spi/topic/fsl-dspi', 'spi/topic/gpio', ↵Mark Brown2015-06-184-92/+264
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | 'spi/topic/imx' and 'spi/topic/orion' into spi-next
| | | | * | | spi: orion: Fix extended baud rates for each Armada SoCsGregory CLEMENT2015-05-271-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit df59fa7f4bca "spi: orion: support armada extended baud rates" made the assumptions that all the Armada SoCs supported the same maximum frequency. However, according the hardware datasheet, the maximum frequency supported by the Armada 370 SoC is tclk/4, for the Armada XP, Armada 38x and Armada 39x SoCs the limitation is 50MHz and for the Armada 375 it is tclk/15. This patch introduces new compatible strings to handle all these case. In order to be future proof a compatible was created for each SoC even if currently some SoCs seem using the same IP. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * | | | spi: imx: Constify platform_device_idKrzysztof Kozlowski2015-05-011-1/+1
| | | | |/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform_device_id is not modified by the driver and core uses it as const. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * / | | spi: Allow compile test of GPIO consumers if !GPIOLIBGeert Uytterhoeven2015-05-061-2/+2
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO subsystem provides dummy GPIO consumer functions if GPIOLIB is not enabled. Hence drivers that depend on GPIOLIB, but use GPIO consumer functionality only, can still be compiled if GPIOLIB is not enabled. Relax the dependency on GPIOLIB if COMPILE_TEST is enabled, where appropriate. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | spi: fsl-dspi: Use pinctrl PM helpersMirza Krak2015-06-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for "sleep" state of pinctrl. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | spi: spi-fsl-dspi: Change the way of increasing spi_message->actual_lengthHaikun Wang2015-06-091-33/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current driver, we increase actual_length in the following way: message->actual_length += dspi_xxx_transfer() It has two defects. First, transmitting maybe in process when the function call finished and we don't know the transmitting result in this moment. Secondly, the last sentence in function before returning is accessing the SPI register and trigger the data transmitting. If we enable interrupt, interrupt may be generated before function return and we also have the same sentence "message->actual_length += dspi_xxx_transfer()" in the IRQ handler. And usually dspi_xxx_transfer will trigger a new IRQ. The original dspi_xxx_transfer call may return when no new IRQ generate. This may mess the variable spi_message->actual_length. Now we increase the variable in the IRQ handler and only when we get the TCF or EOQ interrupt And we get the transmitted data length from the SPI transfer counter instead of the function return value. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | spi: spi-fsl-dspi: Enable TCF interrupt mode supportHaikun Wang2015-06-091-76/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSPI module has two optional interrupts when complete data transfer. One is EOQ interrupt, the other one is TCF interrupt. EOQ indicates a queue of data frame has been transmitted. TCF indicates a frame has been transmitted. This patch enable support TCF mode. Driver binds a correct interrupt mode to every compatible string. User should use the correct compatible string in the dts node. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | Merge branch 'fix/fsl-dspi' of ↵Mark Brown2015-06-0929-887/+1456
| |\ \ \ \ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-fsl-dspi
| * | | | | spi: spi-fsl-dspi: remove clk reference when regmap_mmio initializeHaikun Wang2015-04-241-1/+1
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is unnecessary for DSPI to enable/disable clk when access DSPI register. And it will reduce efficiency. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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*---. \ \ \ \ Merge remote-tracking branches 'spi/topic/ath79', 'spi/topic/atmel' and ↵Mark Brown2015-06-183-32/+296
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | 'spi/topic/davinci' into spi-next
| | | * | | | | spi: davinci: change the lower limit of pre-scale divider to 1Murali Karicheri2015-06-101-1/+1
| | | | |_|/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI hardware spec for Keystone specify a lower value of 0 for pre-scale divider which determine what max value of spi clock (spi-max-frequency) the device can support. This translates to a clock divider of 2. So fix the lower limit value used for the boundary check in davinci_spi_get_prescale() function to 1 so that a maximum of spi device clock rate / 2 is possible to be set for spi-max-frequency. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | | | | spi: atmel: add support to FIFOsCyrille Pitchen2015-06-161-10/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs. When FIFOs are enabled, they can either work in SINGLE data mode or MULTIPLE data mode. The selected mode depends on the configuration of the SPI controller (see below). In SINGLE data mode (or legacy mode), for a single I/O access, only one data can be read from the Receive Data Register (RDR) or written into the Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up to 4 data can be read from the RDR or up 2 data can be written into the TDR in a single 32bit I/O access. So programmers should take good care of the width of the I/O access to read/write the right number of data. The exact number of read/written data depends on both the I/O access width and the data width (from 8 up to 16 bits). To enable the FIFO feature a "atmel,fifo-size" property must be set to provide the maximum number of data (not bytes) the RX and TX FIFOs can store. Hence a 32 data FIFO can always store up to 32 data unrelated with the actual data width. When FIFOs are enabled, the RX one is forced to operate in SINGLE data mode because this driver configures the spi controller as a master. In master mode only, the Received Data Register has an additionnal Peripheral Chip Select field, which prevents us from reading more than a single data at each register access. Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a 8bit data size is used, only two data by access could be written into the Transmit Data Register. Indeed the first data has to be written into the lowest 16 bits whereas the second data has to be written into the highest 16 bits of the TDR. When DMA transfers are used to send data, we don't rework the transmit buffer to cope with this hardware limitation: the additional copies required to prepare a new input buffer suited to both the DMA controller and the spi controller would waste all the benefit of the DMA transfer. Instead, the DMA controller is configured to write only one data at time into the TDR. In pio mode, two data are written in the TDR in a single access. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | | | | spi: atmel: add support for the internal chip-select of the spi controllerCyrille Pitchen2015-06-091-9/+28
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch relies on the CSAAT (Chip Select Active After Transfer) feature introduced by the version 2 of the spi controller. This new mode allows to use properly the internal chip-select output pin of the spi controller instead of using external gpios. Consequently, the "cs-gpios" device-tree property becomes optional. When the new CSAAT bit is set into the Chip Select Register, the internal chip-select output pin remains asserted till both the following conditions become true: - the LASTXFER bit is set into the Control Register (or the Transmit Data Register) - the Transmit Data Register and its shift register are empty. WARNING: if the LASTXFER bit is set into the Control Register then new data are written into the Transmit Data Register fast enough to keep its shifter not empty, the chip-select output pin remains asserted. Only when the shifter becomes empty, the chip-select output pin is unasserted. When the CSAAT bit is clear in the Chip Select Register, the LASTXFER bit is ignored in both the Control Register and the Transmit Data Register. The internal chip-select output pin remains active as long as the Transmit Data Register or its shift register are not empty. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: spi-ath79: Set the initial state of CS0Alban Bedel2015-04-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The internal chip select CS0 wasn't initialized properly to work with CS HIGH chips. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: spi-ath79: Use clk_prepare_enable and clk_disable_unprepareAlban Bedel2015-04-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clocks should be prepared and unprepared, fix this by using clk_prepare_enable() and clk_disable_unprepare() instead of clk_enable() and clk_disable(). Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: spi-ath79: Add device tree supportAlban Bedel2015-04-271-9/+11
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the OF node of the spi controller and use the generic GPIO based chip select instead of the custom controller data. As the controller data isn't used by any board just drop it. Signed-off-by: Alban Bedel <albeu@free.fr> Signed-off-by: Mark Brown <broonie@kernel.org>
* | | | | Merge remote-tracking branch 'spi/topic/omap2-mcspi' into spi-nextMark Brown2015-06-181-146/+134Star
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| * | | | | spi: omap2-mcspi: Handle error on gpio_requestMichael Welling2015-05-251-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a valid GPIO is specified but cannot be requested by the driver, print a message and error out of omap2_mcspi_setup. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: omap2-mcspi: Fix GPIO chip select supportMichael Welling2015-05-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP2_MCSPI_CHCONF_FORCE must be toggled even when using GPIO chip selects. This patch conditionally calls the omap2_mcspi_set_cs function to do so when using GPIO chip selects. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: omap2-mcspi: Fix set_cs function for active highMichael Welling2015-05-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core spi driver swaps the polarity of the enable based on SPI_CS_HIGH. The omap2 controller has an internal configuration register bit called OMAP2_MCSPI_CHCONF_EPOL to handle active high chip selects as well. So we have to revert swap the polarity back for the correct setting of the OMAP2_MCSPI_CHCONF_FORCE bit in omap2_mcspi_set_cs. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: omap2-mcspi: Remove unnecessary delayMichael Welling2015-05-251-3/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core spi driver handles the delay between transactions. This is a remanant from the transfer_one conversion. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: omap2-mcspi: Fix native cs with new set_csMichael Welling2015-05-121-22/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO chip select patch series appears to have broken the native chip select support. This patch pulls the manual native chip select toggling out of the transfer_one routine and adds a set_cs routine. Tested natively on AM3354 with SPI serial flash on spi0cs0. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Michael Welling <mwelling@ieee.org> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: omap2-mcspi: Add gpio_request and init CSMichael Welling2015-05-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If GPIO chip select is specified, request the GPIO in the setup function and release it in the cleanup function. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
| * | | | | spi: omap2-mcspi: Switch driver to use transfer_oneMichael Welling2015-05-081-134/+110Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switches from transfer_one_message to transfer_one to prepare driver for use of GPIO chip selects. Signed-off-by: Michael Welling <mwelling@ieee.org> Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-07-16 03:33:26 +0200