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| * | | clk: zx296718: export I2S mux clocksShawn Guo2017-06-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export I2S mux clocks, so that device tree can refer to them for setting a better parent clock for I2S work clock. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: imx7d: create clocks behind rawnand clock gateStefan Agner2017-06-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun2017-06-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds more clocks for hi3660, including: - video encoder and decoder - ISP (Image Signal Processing) Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: qcom: Add DT bindings for ipq8074 gcc clock controllerAbhishek Sahu2017-06-201-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the compatible strings and the include file for ipq8074 gcc clock controller. Acked-by: Rob Herring <robh@kernel.org> (bindings) Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: add DT bindings header for Gemini clock controllerLinus Walleij2017-06-201-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT binding macros used by the clock controller. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | reset: add DT bindings header for Gemini reset controllerLinus Walleij2017-06-201-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT binding macros used by the reset controller. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd2017-06-171-0/+10
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
| * \ \ \ Merge branch 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm ↵Stephen Boyd2017-06-161-0/+146
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next * 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm: clk: ti: omap4: add clkctrl clock data dt-bindings: clk: add omap4 clkctrl definitions clk: ti: add support for clkctrl clocks Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks
| | * | | | dt-bindings: clk: add omap4 clkctrl definitionsTero Kristo2017-06-151-0/+146
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Contains offsets for all omap4 clkctrl main and optional clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
| * | | | Merge tag 'sunxi-clk-for-4.13' of ↵Stephen Boyd2017-06-165-0/+273
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches from Maxime Ripard: Some new clock units are supported, for the display clocks unsed in the newer SoCs, and the A83T PRCM. There is also a bunch of minor fixes for clocks that are not used by anyone, and reworks needed by drivers that will land in 4.13. * tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits) clk: sunxi-ng: Move all clock types to a library clk: sunxi-ng: a83t: Add support for A83T's PRCM dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t clk: sunxi-ng: a83t: Fix audio PLL divider offset clk: sunxi-ng: a83t: Fix PLL lock status register offset clk: sunxi-ng: Add driver for A83T CCU clk: sunxi-ng: Support multiple variable pre-dividers dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: sun5i: Export video PLLs clk: sunxi-ng: mux: Re-adjust parent rate clk: sunxi-ng: mux: Change pre-divider application function prototype clk: sunxi-ng: mux: split out the pre-divider computation code clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT clk: sunxi-ng: div: Switch to divider_round_rate clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate clk: divider: Make divider_round_rate take the parent clock clk: sunxi-ng: explicitly include linux/spinlock.h clk: sunxi-ng: add support for DE2 CCU ...
| | * | | | clk: sunxi-ng: Add driver for A83T CCUChen-Yu Tsai2017-06-072-0/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Also, the MMC2 module clock supports switching to a "new timing" mode. This mode divides the clock output by half, and disables the CCU based clock delays. The MMC controller must be configure to the same mode, and then use its internal clock delays. This driver does not support runtime switching of the timing modes. Instead, the new timing mode is enforced at probe time. Consumers can check which mode is active by trying to get the current phase delay of the MMC2 phase clocks, which will return -ENOTSUPP if the new timing mode is active. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | clk: sunxi-ng: sun5i: Export video PLLsMaxime Ripard2017-06-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
| | * | | | dt-bindings: add binding for the Allwinner DE2 CCUIcenowy Zheng2017-06-072-0/+32
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | | | Merge branch 'clk-fixes' into clk-nextStephen Boyd2017-06-152-0/+4
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
| * | | | Merge tag 'clk-v4.13-samsung' of ↵Stephen Boyd2017-06-141-0/+3
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull samsung clk driver updates from Sylwester Nawrocki - conversion to the clk_hw API - definitions and fixes of exynos5420 SoC audio subsystem related clocks * tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos542x: Add EPLL rate table clk: samsung: Add missing exynos5420 audio related clocks clk: samsung: Add enable/disable operation for PLL36XX clocks clk: samsung: s5pv210-audss: Convert to the new clk_hw API clk: samsung: exynos-clkout: Convert to the new clk_hw API clk: samsung: exynos-audss: Convert to the new clk_hw API clk: samsung: Convert common drivers to the new clk_hw API clk: samsung: Add local variable to match its purpose clk: samsung: Remove dead code
| | * | | | clk: samsung: Add missing exynos5420 audio related clocksSylwester Nawrocki2017-06-091-0/+3
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | | | Merge tag 'v4.13-rockchip-clk1' of ↵Stephen Boyd2017-06-143-0/+331
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk table and the usual bunch of some new clock-ids and some clocks marked as critical. * tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark some special clk as critical on rk3368 clk: rockchip: mark noc and some special clk as critical on rk3288 clk: rockchip: mark noc and some special clk as critical on rk3228 clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036 clk: rockchip: add clock controller for rk3128 dt-bindings: add bindings for rk3128 clock controller clk: rockchip: export more rk3228 clocks ids clk: rockchip: add ids for rk3399 testclks used for camera handling clk: rockchip: add dt-binding header for rk3128 clk: rockchip: fix up the RK3228 clk cpu setting table clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399
| | * | | | clk: rockchip: add dt-binding header for rk3128Elaine Zhang2017-06-021-0/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the dt-bindings header for the rk3128, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for rk3128. And it also applies to the RK3126 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | | | Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd2017-06-021-1/+9
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Amlogic clock driver updates from Jerome Brunet: * Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks * tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: Add EE 32K Clock for CEC clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 clk: meson: meson8b: mark clk81 as critical clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
| * | | | | | clk: renesas: Add r8a7794 CPG Core Clock DefinitionsGeert Uytterhoeven2017-05-241-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add all R-Car E2 Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2d ("List of Clocks [R-Car E2]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | | | | | clk: renesas: Add r8a7793 CPG Core Clock DefinitionsGeert Uytterhoeven2017-05-241-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add all R-Car M2-N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | | | | | clk: renesas: Add r8a7792 CPG Core Clock DefinitionsGeert Uytterhoeven2017-05-241-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add all R-Car V2H Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2c ("List of Clocks [R-Car V2H]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | | | | | clk: renesas: Add r8a7791 CPG Core Clock DefinitionsGeert Uytterhoeven2017-05-241-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add all R-Car M2-W Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [R-Car M2-W/M2-N]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
| * | | | | | clk: renesas: Add r8a7790 CPG Core Clock DefinitionsGeert Uytterhoeven2017-05-241-0/+52
| | |_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add all R-Car H2 Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2a ("List of Clocks [R-Car H2]") of the R-Car Gen2 Hardware User's Manual rev. 2.00. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
* | | | | | Merge tag 'armsoc-dt64' of ↵Linus Torvalds2017-07-042-0/+169
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "Device-tree updates for arm64 platforms. For the first time I can remember, this is actually larger than the corresponding branch for 32-bit platforms overall, though that has more individual changes. A significant portion this time is due to added machine support: - Initial support for the Realtek RTD1295 SoC, along with the Zidoo X9S set-top-box - Initial support for Actions Semi S900 and the Bubblegum-96 single-board-cёmputer. - Rockchips support for the rk3399-Firefly single-board-computer gets added, this one stands out for being relatively fast, affordable and well₋supported, compared to many boards that only fall into one or two of the above categories. - Mediatek gains support for the mt6797 mobile-phone SoC platform and corresponding evaluation board. - Amlogic board support gets added for the NanoPi K2 and S905x LibreTech CC single-board computers and the R-Box Pro set-top-box - Allwinner board support gets added for the OrangePi Win, Orangepi Zero Plus 2, NanoPi NEO2 and Orange Pi Prime single board computers and the SoPine system-on-module. - Renesas board support for Salvator-XS and H3ULCB automotive development systems. - Socionext Uniphier board support for LD11-global and LD20-global, whatever those may be. - Broadcom adds support for the new Stingray communication processor in its iProc family, along with two reference boards. Other updates include: - For the hisicon platform, support for Hi3660-Hikey960 gets extended significantly. - Lots of smaller updates for Renesas, Amlogic, Rockchip, UniPhier, Broadcom, Allwinner, Hisilicon, Qualcomm, Marvell, and NXP" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (243 commits) ARM64: dts: marvell: armada37xx: Fix timer interrupt specifiers Revert "arm64: dts: marvell: add dma-mask in crypto nodes for 7k/8k" arm64: dts: mediatek: don't include missing file ARM64: dts: meson-gxl: Add Libre Technology CC support dt-bindings: arm: amlogic: Add Libre Technology CC board dt-bindings: add Libre Technology vendor prefix arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K arm64: dts: zte: Use - instead of @ for DT OPP entries arm64: dts: marvell: add gpio support for Armada 7K/8K arm64: dts: marvell: add pinctrl support for Armada 7K/8K arm64: dts: marvell: use new binding for the system controller on cp110 arm64: dts: marvell: remove *-clock-output-names on cp110 arm64: dts: marvell: use new bindings for xor clocks on ap806 arm64: dts: marvell: mcbin: enable the mdio node arm64: dts: Add Actions Semi S900 and Bubblegum-96 dt-bindings: Add vendor prefix for uCRobotics arm64: dts: marvell: add xmdio nodes for 7k/8k arm64: dts: marvell: add a comment on the cp110 slave node status arm64: dts: marvell: remove cpm crypto nodes from dts files arm64: dts: marvell: cp110: enable the crypto engine at the SoC level ...
| * \ \ \ \ \ Merge tag 'amlogic-dt64-2' of ↵Arnd Bergmann2017-06-291-1/+9
| |\ \ \ \ \ \ | | | |/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64 Pull "Amlogic 64-bit DT changes for v4.13 (round 2)" from Kevin Hilman: - support new SPI controller driver - several more leaf clocks exposed to DT - New board: S905x LibreTech CC board * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxl: Add Libre Technology CC support dt-bindings: arm: amlogic: Add Libre Technology CC board dt-bindings: add Libre Technology vendor prefix ARM64: dts: meson-gx: Add SPICC nodes clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
| * | | | | | arm64: dts: Add pinctrl DT nodes for Stingray SOCPramod Kumar2017-06-061-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds pinctrl and pinmux related DT nodes for Stingray SOC. For manageability, pinctrl and pinmum DT nodes are added as separate DTSi file and included in main DTSi file. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Vikram Prakash <vikram.prakash@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | | | | dt-bindings: clk: Extend binding doc for Stingray SOCSandeep Tripathy2017-06-061-0/+101
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update iproc clock dt-binding documentation with Stingray pll and clock details. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | | | | | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2017-07-043-0/+174
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "New SoC specific drivers: - NVIDIA Tegra PM Domain support for newer SoCs (Tegra186 and later) based on the "BPMP" firmware - Clocksource and system controller drivers for the newly added Action Semi platforms (both arm and arm64). Reset subsystem, merged through arm-soc by tradition: - New drivers for Altera Stratix10, TI Keystone and Cortina Gemini SoCs - Various subsystem-wide cleanups Updates for existing SoC-specific drivers - TI GPMC (General Purpose Memory Controller) - Mediatek "scpsys" system controller support for MT6797 - Broadcom "brcmstb_gisb" bus arbitrer - ARM SCPI firmware - Renesas "SYSC" system controller One more driver update was submitted for the Freescale/NXP DPAA data path acceleration that has previously been used on PowerPC chips. I ended up postponing the merge until some API questions for its unusual MMIO access are resolved" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits) clocksource: owl: Add S900 support clocksource: Add Owl timer soc: renesas: rcar-sysc: Use GENPD_FLAG_ALWAYS_ON firmware: tegra: Fix locking bugs in BPMP soc/tegra: flowctrl: Fix error handling soc/tegra: bpmp: Implement generic PM domains soc/tegra: bpmp: Update ABI header PM / Domains: Allow overriding the ->xlate() callback soc: brcmstb: enable drivers for ARM64 and BMIPS soc: renesas: Rework Kconfig and Makefile logic reset: Add the TI SCI reset driver dt-bindings: reset: Add TI SCI reset binding reset: use kref for reference counting soc: qcom: smsm: Improve error handling, quiesce probe deferral cpufreq: scpi: use new scpi_ops functions to remove duplicate code firmware: arm_scpi: add support to populate OPPs and get transition latency dt-bindings: reset: Add reset manager offsets for Stratix10 memory: omap-gpmc: add error message if bank-width property is absent memory: omap-gpmc: make dts snippet include semicolon reset: Add a Gemini reset controller ...
| * \ \ \ \ \ Merge tag 'actions-drivers-for-4.13' of ↵Arnd Bergmann2017-06-291-0/+19
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers Pull "Actions Semi SoC drivers for 4.13" from Andreas Färber: This adds clock source and power domain drivers for S500/S900. * tag 'actions-drivers-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: soc: actions: owl-sps: Factor out owl_sps_set_pg() for power-gating soc: actions: Add Owl SPS dt-bindings: power: Add Owl SPS power domains clocksource: owl: Add S900 support clocksource: Add Owl timer
| * \ \ \ \ \ \ Merge tag 'v4.12-next-soc' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson2017-06-191-0/+30
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers - enhance scpsys to support mt6797 - add mt6797 support to scpsys - fix error path in pmic-wrapper - fix possible NULL pointer dereference in pmic-wrapper * tag 'v4.12-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: PMIC wrap: Fix possible NULL derefrence. soc: mediatek: PMIC wrap: Fix error handling soc: mediatek: add MT6797 scpsys support soc: mediatek: add vdec item for scpsys soc: mediatek: avoid using fixed spm power status defines Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | soc: mediatek: add MT6797 scpsys supportMars Cheng2017-05-151-0/+30
| | | |/ / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds scpsys support for MT6797 Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Kevin-CW Chen <kevin-cw.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| * | | | | | | dt-bindings: reset: Add reset manager offsets for Stratix10Richard Gong2017-06-011-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several changes in reset manager offsets from Arria10 to Stratix10. This patch is based on one from Arria10 and adds offset updates for Stratix10 Signed-off-by: Richard Gong <richard.gong@intel.com>
| * | | | | | | reset: add DT bindings header for Gemini reset controllerLinus Walleij2017-05-241-0/+36
| |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the DT binding macros used by the reset controller. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* | | | | | | Merge tag 'armsoc-dt' of ↵Linus Torvalds2017-07-047-1/+138
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM device-tree updates from Arnd Bergmann: "Device-tree continues to see lots of updates. The majority of patches here are smaller changes for new hardware on existing platforms, and there are a few larger changes worth pointing out. New machines: - The new Action Semi S500 platform is added along with initial support for the LeMaker Guitar board. - STM32 gains support for three new boards: stm32h743-disco, stm32f746-disco, and stm32f769-disco, along with new device support for the existing stm32f429 boards. - Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with 10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus board. - On Marvell "mvebu", we gain support for the Linksys WRT3200ACM wireless router. - For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and the Technexion Pico i.MX7D single-board computers. - The BeagleBone Blue is added for OMAP, it's the latest variation of the popular Beaglebone Black single-board computer. - The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are added, these are the latest variations of a seemingly endless supply of similar single-board computers. Other updates: - Linus Walleij improves support for the "Faraday" based SoC platforms from various SoC makers (Moxart, Aspeed, Gemini) - The ARM Mali GPU is now describe on Rockchips SoCs - Mediatek MT7623 is extended significantly, making it much more useful. - Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom, Allwinner, Qualcomm, iMX - For Amlogic, the clock support is extended a lot on meson8b. - We now build the devicetree file for the Raspberry Pi 3 on 32-bit ARM, in addition to the existing ARM64 support, to help users wanting to run a 32-bit system on it" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits) ARM: dts: socfpga: set the i2c frequency ARM: dts: socfpga: Add second ethernet alias to VINING FPGA ARM: dts: socfpga: Drop LED node from VINING FPGA ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA ARM: dts: socfpga: Enable QSPI support on VINING FPGA ARM: dts: socfpga: Fix the ethernet clock phandle ARM: pxa: Use - instead of @ for DT OPP entries ARM: dts: owl-s500: Add SPS node ARM: dts: owl-s500: Set CPU enable-method dt-bindings: arm: cpus: Add S500 enable-method ARM: dts: Add Actions Semi S500 and LeMaker Guitar dt-bindings: arm: Document Actions Semi S900 dt-bindings: timer: Document Owl timer ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes dt-bindings: arm: Document Actions Semi S500 dt-bindings: Add vendor prefix for Actions Semi ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango) ARM: dts: armada-385-linksys: fixup button node names ARM: dts: armada-385-linksys: group pins in pinctrl ...
| * \ \ \ \ \ \ Merge tag 'amlogic-dt-2' of ↵Arnd Bergmann2017-06-292-1/+19
| |\ \ \ \ \ \ \ | | | |_|_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Merge "Amlogic 32-bit DT changes for v4.13 (round 2)" from Kevin Hilman: - greatly expands DT clock support for meson8b * tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (22 commits) ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b ARM: dts: meson8b: add the SCU device node ARM: dts: meson: add USB support on Meson8 and Meson8b ARM: dts: meson: add the hardware random number generator ARM: dts: meson8: add reserved memory zones ARM: dts: meson: add the SAR ADC ARM: dts: meson8: add the pins for the SDIO controller ARM: dts: meson8: add the PWM_E and PWM_F pins ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros ARM: dts: meson: use C preprocessor friendly include syntax ARM: dts: meson8: fix the IR receiver pins clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock ...
| | * | | | | | clk: meson8b: export the ethernet gate clockMartin Blumenstingl2017-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the ethernet gate clock to the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | | clk: meson8b: export the USB clocksMartin Blumenstingl2017-06-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | | clk: meson8b: export the gate clock for the HW random number generatorMartin Blumenstingl2017-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This exports the clock so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | | clk: meson8b: export the SDIO clockMartin Blumenstingl2017-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the SDIO clock so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | | clk: meson8b: export the SAR ADC clocksMartin Blumenstingl2017-06-121-0/+2
| | | |_|/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the clocks for the SAR ADC so they can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | clk: meson-gxbb: un-export the CPU clockMartin Blumenstingl2017-05-291-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU clock defined in the Meson GX clock driver is actually a left-over from the Meson8b clock controller. Un-export the clock so we can remove it from the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | clk: meson-gxbb: expose UART clocksHelmut Klein2017-05-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy the commit message to match similar change] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | clk: meson-gxbb: expose SPICC gateNeil Armstrong2017-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the SPICC gate clock to enable the SPICC controller. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [tidy commit message to match similar changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | clk: meson-gxbb: expose spdif master clockJerome Brunet2017-05-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | clk: meson-gxbb: expose i2s master clockJerome Brunet2017-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose cts_amclk in the device tree bindings Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| | * | | | | clk: meson-gxbb: expose spdif clock gatesJerome Brunet2017-05-291-0/+2
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose the clock gates required for the spdif output Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| * | | | | Merge tag 'renesas-dt-bindings2-for-v4.13' of ↵Olof Johansson2017-06-191-0/+51
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Second Round of Renesas ARM Based SoC DT Bindings Updates for v4.13 * Document: - Add Renesas H3-based Salvator-XS board DT bindings - Add iW-RainboW-G20D-Qseven-RZG1M board - Add iW-RainboW-G20M-Qseven-RZG1M system on module - Update R-Car Gen3 ULCB board part numbers * Add clock bit definitions for r7s72100 SoC * tag 'renesas-dt-bindings2-for-v4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Document Renesas H3-based Salvator-XS board DT bindings ARM: shmobile: Update R-Car Gen3 ULCB board part numbers ARM: shmobile: document iW-RainboW-G20D-Qseven-RZG1M board ARM: shmobile: document iW-RainboW-G20M-Qseven-RZG1M system on module ARM: dts: r7s72100: add clock bit definitions Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | ARM: dts: r7s72100: add clock bit definitionsChris Brandt2017-06-051-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the remaining bit locations for the module stop clock registers. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | | | Merge tag 'v4.13-rockchip-dts32-1' of ↵Olof Johansson2017-06-192-0/+49
| |\ \ \ \ \ \ | | |/ / / / / | |/| | | / / | | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt A bunch of changes including mali gpu nodes for rk3288 boards following (and including) the new Mali Midgard binding; a lot of improvements for the rk3228/rk3229 socs (tsadc, operating points, usb, clock-rates, pinctrl, watchdog); finalizing the rk1108->rv1108 rename and adc buttons for the rk3288 firefly boards. * tag 'v4.13-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: enable usb for rk3229 evb board ARM: dts: rockchip: add usb nodes on rk322x ARM: dts: rockchip: add adc button for Firefly ARM: dts: rockchip: enable ARM Mali GPU on rk3288-veyron ARM: dts: rockchip: enable ARM Mali GPU on rk3288-firefly ARM: dts: rockchip: enable ARM Mali GPU on rk3288-rock2-som ARM: dts: rockchip: add ARM Mali GPU node for rk3288 dt-bindings: gpu: add bindings for the ARM Mali Midgard GPU ARM: dts: rockchip: set a sane frequence for tsadc on rk322x ARM: dts: rockchip: add operating-points-v2 for cpu on rk322x ARM: dts: rockchip: set default rates for core clocks on rk322x ARM: dts: rockchip: add second uart2 pinctrl on rk322x ARM: dts: rockchip: correct rk322x uart2 pinctrl ARM: dts: rockchip: add watchdog device node on rk322x clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399 ARM: dts: rockchip: fix rk322x i2s1 pinctrl error ARM: dts: rockchip: rename RK1108-evb to RV1108-evb ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108 ARM: dts: rockchip: Setup usb vbus-supply on rk3288-rock2 Signed-off-by: Olof Johansson <olof@lixom.net>