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* ASoC: fsl_sai: support more than 2 channelsAlexandre Belloni2017-02-131-2/+2
| | | | | | | | | | | The FSL SAI can support up to 32 channels using TDM. Report that value so they can actually be used. Tested using 8 channels. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl_sai: Use 'np' variableFabio Estevam2016-08-171-3/+3
| | | | | | | | | | The 'np' variable is already assigned to 'pdev->dev.of_node', so use it to improve readability. No functional change. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl_sai: Allow setting the SAI MCLK directionFabio Estevam2016-05-051-0/+20
| | | | | | | | | | | | | | | On mx6ul the General Purpose Register 1 (GPR1) contains the following bits for configuring the direction of the SAI MCLKs: SAI1_MCLK_DIR, SAI2_MCLK_DIR, SAI3_MCLK_DIR Introduce the "fsl,sai-mclk-direction-output" optional property to allow configuring the SAI_MCLK outputs. Tested on a imx6ul-evk board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl_sai: Introduce a compatible string for MX6ULFabio Estevam2016-05-051-1/+3
| | | | | | | | | MX6UL may need to configure the General Purpose Register 1 (GPR1), so it is better to add a new compatible string to differentiate. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge remote-tracking branches 'asoc/topic/fsl-sai', 'asoc/topic/fsl-ssl', ↵Mark Brown2016-03-131-1/+2
|\ | | | | | | 'asoc/topic/hdac' and 'asoc/topic/max9867' into asoc-next
| * ASoC: fsl_sai: Use usleep_range() instead of msleep()Xiubo Li2016-01-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Since msleep() will sleep longer than intended time for values less than 20ms, this patch allows the use of usleep_range for just 1ms. usleep_range is a finer precision implementation of msleep and is designed to be a drop-in replacement for udelay where a precise sleep/busy-wait is unnecessary. More details see Documentation/timers/timers-howto.txt. Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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*-. \ Merge remote-tracking branches 'asoc/topic/dpcm', 'asoc/topic/dwc', ↵Mark Brown2015-12-231-11/+87
|\ \ \ | | | | | | | | | | | | 'asoc/topic/fsl', 'asoc/topic/fsl-asrc' and 'asoc/topic/fsl-esai' into asoc-next
| | * | ASoC: fsl: using params_width function to simplify codeZidan Wang2015-11-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | using params_width function to simplify code. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * | Merge branch 'topic/fsl-sai' of ↵Mark Brown2015-11-251-8/+68
| | |\| | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-fsl
| | | * ASoC: fsl_sai: add tdm slots operation supportZidan Wang2015-11-251-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tdm slots operation support. If tdm slots and slot width have been configured in machine driver, we should use these values. Otherwise, using relevant channels and word length to set slots and slot width. SAI will generate BCLK depends on sample rate, slots and slot width. And there may be unused BCLK cycles before each LRCLK transition. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master modeZidan Wang2015-11-171-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync error sometimes. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | | * ASoC: fsl-sai: don't set bclk for Tx/Rx Synchronous with another SAI modeZidan Wang2015-11-171-2/+14
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | In fsl_sai_set_bclk function, we should not set bclk for Tx/Rx Synchronous with another SAI mode. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * ASoC: fsl-sai: add default register map for regmap cacheZidan Wang2015-11-161-2/+18
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL_SAI_TDR register is writable and not readable. According to regmap_volatile() function, if FSL_SAI_TDR want to be volatile, it should be readable. So we should remove FSL_SAI_TDR from volatile register list. If the flat cache don't have default register map, when do regcache_sync operation, the non volatile and writable registers will be synchronised to 0. FSL_SAI_TDR reigster will be written a 0 and cause channel swap. So add default register map for flat cache, and such register will not be written. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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*-. \ Merge remote-tracking branches 'asoc/fix/davinci', 'asoc/fix/es8328', ↵Mark Brown2015-12-231-0/+18
|\ \ \ | | |/ | |/| | | | 'asoc/fix/fsl-sai', 'asoc/fix/rockchip', 'asoc/fix/sgtl5000' and 'asoc/fix/wm8974' into asoc-linus
| | * ASoC: fsl_sai: fix no frame clk in master modeZidan Wang2015-12-181-0/+18
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After several open/close sai test with ctrl+c, there will be I/O error. The SAI can't work anymore, can't recover. There will be no frame clock. With adding the software reset in trigger stop, the issue can be fixed. This is a hardware bug/errata and reset is the only option. According to the reference manual, the software reset doesn't reset any control register but only internal hardware logics such as bit clock generator, status flags, and FIFO pointers. (Our purpose is just to reset the clock generator while the software reset is the only way to do that.) Since slave mode doesn't use the clock generator, only apply the reset procedure to the master mode. For asynchronous mode, TX will not be reset when RX is still running. In this case, i can't reproduce this issue. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | Merge remote-tracking branches 'asoc/fix/davinci', 'asoc/fix/es8328', ↵Mark Brown2015-11-251-1/+2
|\ \ | |/ |/| | | 'asoc/fix/fsl', 'asoc/fix/fsl-sai' and 'asoc/fix/intel' into asoc-linus
| * ASoC: fsl_sai: fix Rx synchrounous modeStefan Agner2015-10-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using the Rx clock for both, transmitter and receiver, the transmitter needs to be set to synchronous with receiver. This reverts 855675f6e6a6 ("ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous Mode"), which, judiging from the commit log, seems to mixed up between the two synchronous modes: The boolean sai->synchronous[TX] is indicating wheather the SAI should work in Rx synchronous mode (sync Tx with Rx), hence if the value is true, the SYNC field of TCR2 needs to be set to 0x1 ("Synchronous with receiver"). Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | ASoC: fsl: Use #ifdef instead of #if for CONFIG_PM_SLEEPNicolin Chen2015-10-261-1/+1
| | | | | | | | | | | | | | | | Change them to #ifdef as CONFIG_PM_SLEEP might not be defined at all. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | Merge branch 'topic/fsl-mega-fast' of ↵Mark Brown2015-10-261-0/+33
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-fsl
| * | ASoC: fsl_sai: Add driver suspend and resume to support MEGA FastZidan Wang2015-10-051-0/+33
| |/ | | | | | | | | | | | | | | | | | | | | For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of modules during system suspend and resume procedure. Thus, SAI needs to save all the values of registers before the system suspend and restore them after the system resume. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | ASoC: fsl_sai: Constify rate constraintsLars-Peter Clausen2015-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rate constraints in this driver are shared between all device instances. It should not be (and is not) modified at runtime, so make them const. While we are at it also change the type of the rates array from u32 to unsigned int. While both resolve to the same type, u32 is usually used to empathize that the value is for a 32-bit hardware register or similar which makes it slightly confusing in this context. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* | ASoC: fsl_sai: Fix module autoload for OF platform driverLuis de Bethencourt2015-09-141-0/+1
|/ | | | | | | | This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt <luis@debethencourt.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl: Add dedicated DMA buffer size for each cpu daiShengjiu Wang2015-07-071-1/+1
| | | | | | | | | | | | As the ssi is not the only cpu dai, there are esai, spdif, sai. and imx_pcm_dma can be used by all of them. Especially ESAI need a larger DMA buffer size. So Add dedicated DMA buffer for each cpu dai. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Timur Tabi <timur@tabi.org> Signed-off-by: Mark Brown <broonie@kernel.org>
*-. Merge remote-tracking branches 'asoc/topic/fsl', 'asoc/topic/fsl-sai', ↵Mark Brown2015-06-051-6/+135
|\ \ | | | | | | | | | 'asoc/topic/fsl-spdif', 'asoc/topic/fsl-ssi' and 'asoc/topic/gpio-jack' into asoc-next
| | * ASoC: fsl_sai: add 12kHz, 24kHz, 176.4kHz and 192kHz sample rate supportZidan Wang2015-05-121-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Normally we don't support 12kHz, 24kHz in audio driver, alsa didn't have formal definition of 12kHz, 24kHz, but alsa supply a way to support these sample rates. And add 176.4kHz and 192kHz support. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
| | * ASoC: fsl_sai: add sai master mode supportZidan Wang2015-05-121-3/+114
| |/ | | | | | | | | | | | | | | | | | | | | | | | | When sai works on master mode, set its bit clock and frame clock. SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk will select proper MCLK source, then calculate and set the bit clock divider. After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add hw_free() to disable the mclk. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* / ASoC: dmaengine_pcm: Make FLAG_NO_RESIDUE internalLars-Peter Clausen2015-04-271-2/+1Star
|/ | | | | | | | | | | | | | | | | | | | | | Whether residue can be reported or not is not a property of the audio controller but of the DMA controller. The FLAG_NO_RESIDUE was initially added when the DMAengine framework had no support for describing the residue reporting capabilities of the controller. Support for this was added quite a while ago and recently the DMAengine framework started to complain if a driver does not describe its capabilities and a lot of patches have been merged that add support for this where it was missing. So it should be safe to assume that driver on actively used platforms properly implement the DMA capabilities API. This patch makes the FLAG_NO_RESIDUE internal and no longer allows audio controller drivers to manually set the flag. If a DMA driver against expectations does not support reporting its capabilities for now the generic DMAengine PCM driver will now emit a warning and simply assume that residue reporting is not supported. In the future this might be changed to aborting with an error. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl_sai: Make error message conciseFabio Estevam2015-01-081-1/+1
| | | | | | | | | | | Currently the error message uses 'np->full_name' which leads to a very verbose log that contains the full path of the node. We can have a concise log by using pdev->name instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* ASoC: fsl: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0Star
| | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.Xiubo Li2014-09-011-3/+3
| | | | | | | | | | | | | | | | | | | | The 'big-endian-data' property is originally used to indicate whether the LSB firstly or MSB firstly will be transmitted to the CODEC or received from the CODEC, and there has nothing relation to the memory data. Generally, if the audio data in big endian format, which will be using the bytes reversion, Here this can only be used to bits reversion. So using the 'lsb-first' instead of 'big-endian-data' can make the code to be readable easier and more easy to understand what this property is used to do. This property used for configuring whether the LSB or the MSB is transmitted first for the fifo data. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* Merge branch 'topic/fsl' of ↵Mark Brown2014-09-011-5/+1Star
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-fsl-sai
| * ASoC: fsl-sai: Convert to use regmap framework's endianness method.Xiubo Li2014-08-271-5/+1Star
| | | | | | | | | | Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous ModeNicolin Chen2014-08-171-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one design rule according to SAI's reference manual: If the transmitter bit clock and frame sync are to be used by both transmitter and receiver, the transmitter must be configured for asynchronous operation and the receiver for synchronous operation. And SYNC of TCR2 is a 2-width control bit: 00 Asynchronous mode. 01 Synchronous with receiver. 10 Synchronous with another SAI transmitter. 11 Synchronous with another SAI receiver. So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC bit of RCR2 to 0x1 (Synchronous with transmitter). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Make Synchronous and Asynchronous modes exclusiveNicolin Chen2014-08-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The previous patch (ASoC: fsl_sai: Add asynchronous mode support) added new Device Tree bindings for Asynchronous and Synchronous modes support. However, these two shall not be present at the same time. So this patch just simply makes them exclusive so as to avoid incorrect Device Tree binding usage. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Add asynchronous mode supportNicolin Chen2014-08-171-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SAI supports these operation modes: 1) asynchronous mode Both Tx and Rx are set to be asynchronous. 2) synchronous mode (Rx sync with Tx) Tx is set to be asynchronous, Rx is set to be synchronous. 3) synchronous mode (Tx sync with Rx) Rx is set to be asynchronous, Tx is set to be synchronous. 4) synchronous mode (Tx/Rx sync with another SAI's Tx) 5) synchronous mode (Tx/Rx sync with another SAI's Rx) * 4) and 5) are beyond this patch because they are related with another SAI. As the initial version of this SAI driver, it supported 2) as default while the others were totally missing. So this patch just adds supports for 1) and 3). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Set SYNC bit of TCR2 to Asynchronous ModeNicolin Chen2014-08-171-2/+1Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is one design rule according to SAI's reference manual: If the transmitter bit clock and frame sync are to be used by both transmitter and receiver, the transmitter must be configured for asynchronous operation and the receiver for synchronous operation. And SYNC of TCR2 is a 2-width control bit: 00 Asynchronous mode. 01 Synchronous with receiver. 10 Synchronous with another SAI transmitter. 11 Synchronous with another SAI receiver. So the driver should have set SYNC bit of TCR2 to 0x0, and meanwhile set SYNC bit of RCR2 to 0x1 (Synchronous with transmitter). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Initialize with software resetNicolin Chen2014-08-171-2/+7
|/ | | | | | | | | This patch adds software reset code in dai_probe() so as to make a true init by clearing SAI's internal logic, including the bit clock generation, status flags, and FIFO pointers. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
*-. Merge remote-tracking branches 'asoc/topic/fsl', 'asoc/topic/fsl-asrc', ↵Mark Brown2014-08-041-0/+2
|\ \ | | | | | | | | | 'asoc/topic/fsl-spdif' and 'asoc/topic/imx-audmux' into asoc-next
| * | ASoC: fsl_sai: Add stream names for DPCM usageNicolin Chen2014-07-311-0/+2
| |/ | | | | | | | | | | | | | | | | | | DPCM needs extra dapm routes in the machine driver to route audio between Front-End and Back-End. In order to differ the stream names in the route map from CODECs, we here add specific stream names to SAI driver so that we can implement ASRC via DPCM to it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Improve enable flow in fsl_sai_trigger()Nicolin Chen2014-07-251-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous enable flow: 1, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 2, Mask IRQ of Tx/Rx to enable its interrupt. 3, Enable DMA request of Tx/Rx. As this flow would enable DMA request later than TERE, the Tx FIFO would be easily emptied into underrun while Rx FIFO would be easily stuffed into overrun due to the delayed DMA transfering. This issue happened merely occational before the patch 'ASoC: fsl_sai: Reset FIFOs after disabling TE/RE' because there were useless data remaining in the FIFO for the gap. However, it manifested after FIFO reset's implemented. After this patch, the new flow: 1, Enable DMA request of Tx/Rx. 2, Enable TE&RE (SAI starts to consume tx FIFO and feed rx FIFO) 3, Mask IRQ of Tx/Rx to enable its interrupt. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Don't reset FIFO until TE/RE bit is unsetNicolin Chen2014-07-251-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | TE/RE bit of T/RCSR will remain set untill the current frame is physically finished. The FIFO reset operation should wait this bit's totally cleared rather than ignoring its status which might cause TE/RE disabling failed. This patch adds delay and timeout to wait for its completion before FIFO reset. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Reduce race condition during TE/RE enablingNicolin Chen2014-07-251-11/+7Star
| | | | | | | | | | | | | | | | | | | | | | | | For trigger start, we don't need to check if it's the first time to enable TE/RE or second time. It doesn't hurt to enable them any way, which in the meantime can reduce race condition for TE/RE enabling. For trigger stop, we will definitely clear FRDE of current direction. Thus the driver only needs to read the opposite one's. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Fix incorrect register writing in fsl_sai_isr()Nicolin Chen2014-07-171-1/+1
| | | | | | | | | | | | | | In the rx irq handling part, we should clear the flags in RCSR not TCSR. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* | ASoC: fsl_sai: Reset FIFOs after disabling TE/RENicolin Chen2014-07-171-2/+5
|/ | | | | | | | SAI will not clear their FIFOs after disabling TE/RE. Therfore, the driver should take care the task so as not to let useless data remain in the FIFO. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Use FSL_SAI_xXR() and regmap_update_bits() to simplify codeNicolin Chen2014-04-141-76/+25Star
| | | | | | | By doing this, the driver can drop around 50 lines and become neater. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Fix incorrect condition check in trigger()Nicolin Chen2014-04-141-1/+2
| | | | | | | | | | | | Patch ASoC: fsl_sai: Fix buggy configurations in trigger() doesn't entirely fix the condition: FRDE of the current substream direction is being cleared while the code is still using the non-updated one. Thus this patch fixes this issue by checking the opposite one's FRDE alone since the current one's is absolutely disabled. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Add clock controls for SAINicolin Chen2014-04-141-2/+36
| | | | | | | | | | | | | | | | | | | | | | The SAI mainly has the following clocks: bus clock control and configure registers and to generate synchronous interrupts and DMA requests. mclk1, mclk2, mclk3 to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. So this patch adds these clocks and their clock controls to the driver. [ To concern the old DTB cases, I've added a bit of extra code to make the driver compatible with them. And by marking clock NULL if failed to get, the clk_prepare() or clk_get_rate() would easily return 0 so no further path should be broken. -- by Nicolin ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Add imx6sx platform supportNicolin Chen2014-04-141-2/+10
| | | | | | | | | | | The next coming i.MX6 Solo X SoC also contains SAI module while we use imp_pcm_init() for i.MX platform. So this patch adds one compatible route for imx6sx and updates the DT doc accordingly. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streamsNicolin Chen2014-04-141-2/+6
| | | | | | | | | | | We only enable one side interrupt for each stream since over/underrun on the opposite stream would be resulted from what we previously did, enabling TERE but remaining FRDE disabled, even though the xrun on the opposite direction will not break the current stream. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
* ASoC: fsl_sai: Fix buggy configurations in trigger()Nicolin Chen2014-04-141-18/+17Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current trigger() has two crucial problems: 1) The DMA request enabling operations (FSL_SAI_CSR_FRDE) for Tx and Rx are now totally exclusive: It would fail to run simultaneous Tx-Rx cases. 2) The TERE disabling operation depends on an incorrect condition -- active reference count that only gets increased in snd_pcm_open() and decreased in snd_pcm_close(): The TERE would never get cleared. So this patch overwrites the trigger function by following these rules: A) We continue to support tx-async-while-rx-sync-to-tx case alone, which's originally limited by this fsl_sai driver, but we make the code easy to modify for the further support of the opposite case. B) We enable both TE and RE for PLAYBACK stream or CAPTURE stream but only enabling the DMA request bit (FSL_SAI_CSR_FRDE) of the current direction due to the requirement of SAI -- For tx-async-while-rx-sync-to-tx case, the receiver is enabled only when both the transmitter and receiver are enabled. Tested cases: a) aplay test.wav -d5 b) arecord -r44100 -c2 -fS16_LE test.wav -d5 c) arecord -r44100 -c2 -fS16_LE -d5 | aplay d) (aplay test2.wav &); sleep 1; arecord -r44100 -c2 -fS16_LE test.wav -d1 e) (arecord -r44100 -c2 -fS16_LE test.wav -d5 &); sleep 1; aplay test.wav -d1 Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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