From a92b83af289002080d47ff89269047ed84952729 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 5 Jun 2013 10:02:54 -0500 Subject: ARM: socfpga: dts: Add gate-clock bindings Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed the peripherals. Signed-off-by: Dinh Nguyen Reviewed-by: Pavel Machek CC: Arnd Bergmann CC: Olof Johansson Cc: Pavel Machek CC: Signed-off-by: Olof Johansson --- Documentation/devicetree/bindings/clock/altr_socfpga.txt | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings/clock/altr_socfpga.txt') diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index bd0c8416a5c8..0045433eae1f 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -9,6 +9,9 @@ Required properties: "altr,socfpga-pll-clock" - for a PLL clock "altr,socfpga-perip-clock" - The peripheral clock divided from the PLL clock. + "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and + can get gated. + - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - clocks : shall be the input parent clock phandle for the clock. This is either an oscillator or a pll output. @@ -16,3 +19,7 @@ Required properties: Optional properties: - fixed-divider : If clocks have a fixed divider value, use this property. +- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register + and the bit index. +- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift, + and width. -- cgit v1.2.3-55-g7522