From 52958be3ad6e2b72a5943718f339ed4e11685739 Mon Sep 17 00:00:00 2001 From: Cyril Chemparathy Date: Thu, 25 Mar 2010 17:43:47 -0400 Subject: Davinci: support LPSC SwRstDisable state The current clock control code always gates the clock (PSC state Disable = 2) on clk_disable(). Some on-chip peripherals (e.g. LCD controller on TNETV107X) need to be put into SwRstDisable = 0 on clock disable, to maintain hardware sanity. This patch extends the davinci_psc_config() arguments to pass in the desired module state instead of a boolean enable/disable. Further, clk_disable() now checks for the PSC_SWRSTDISABLE clk flag before selecting the target state. Signed-off-by: Cyril Chemparathy Signed-off-by: Kevin Hilman --- arch/arm/mach-davinci/clock.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-davinci/clock.h') diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index aa0a61150325..53a0f7b90119 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h @@ -101,10 +101,11 @@ struct clk { /* Clock flags: SoC-specific flags start at BIT(16) */ #define ALWAYS_ENABLED BIT(1) -#define CLK_PSC BIT(2) -#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ +#define CLK_PSC BIT(2) +#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ #define CLK_PLL BIT(4) /* PLL-derived clock */ -#define PRE_PLL BIT(5) /* source is before PLL mult/div */ +#define PRE_PLL BIT(5) /* source is before PLL mult/div */ +#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */ #define CLK(dev, con, ck) \ { \ -- cgit v1.2.3-55-g7522