From 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Sat, 16 Apr 2005 15:20:36 -0700 Subject: Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip! --- arch/arm/mach-lh7a40x/irq-lpd7a40x.c | 128 +++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 arch/arm/mach-lh7a40x/irq-lpd7a40x.c (limited to 'arch/arm/mach-lh7a40x/irq-lpd7a40x.c') diff --git a/arch/arm/mach-lh7a40x/irq-lpd7a40x.c b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c new file mode 100644 index 000000000000..6262d449120c --- /dev/null +++ b/arch/arm/mach-lh7a40x/irq-lpd7a40x.c @@ -0,0 +1,128 @@ +/* arch/arm/mach-lh7a40x/irq-lpd7a40x.c + * + * Copyright (C) 2004 Coastal Environmental Systems + * Copyright (C) 2004 Logic Product Development + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + + +static void lh7a40x_ack_cpld_irq (u32 irq) +{ + /* CPLD doesn't have ack capability */ +} + +static void lh7a40x_mask_cpld_irq (u32 irq) +{ + switch (irq) { + case IRQ_LPD7A40X_ETH_INT: + CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4; + break; + case IRQ_LPD7A400_TS: + CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8; + break; + } +} + +static void lh7a40x_unmask_cpld_irq (u32 irq) +{ + switch (irq) { + case IRQ_LPD7A40X_ETH_INT: + CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4; + break; + case IRQ_LPD7A400_TS: + CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8; + break; + } +} + +static struct irqchip lh7a40x_cpld_chip = { + .ack = lh7a40x_ack_cpld_irq, + .mask = lh7a40x_mask_cpld_irq, + .unmask = lh7a40x_unmask_cpld_irq, +}; + +static void lh7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc, + struct pt_regs *regs) +{ + unsigned int mask = CPLD_INTERRUPTS; + + desc->chip->ack (irq); + + if ((mask & 0x1) == 0) /* WLAN */ + IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT); + + if ((mask & 0x2) == 0) /* Touch */ + IRQ_DISPATCH (IRQ_LPD7A400_TS); + + desc->chip->unmask (irq); /* Level-triggered need this */ +} + + + /* IRQ initialization */ + +void __init lh7a40x_init_board_irq (void) +{ + int irq; + + /* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs. + PF7 supports the CPLD. + Rev B (v3.4): PF0, PF1, and PF2 are available IRQs. + PF3 supports the CPLD. + (Some) LPD7A404 prerelease boards report a version + number of 0x16, but we force an override since the + hardware is of the newer variety. + */ + + unsigned char cpld_version = CPLD_REVISION; + int pinCPLD; + +#if defined CONFIG_MACH_LPD7A404 + cpld_version = 0x34; /* Override, for now */ +#endif + pinCPLD = (cpld_version == 0x28) ? 7 : 3; + + /* First, configure user controlled GPIOF interrupts */ + + GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */ + GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */ + GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */ + barrier (); + GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */ + + /* Then, configure CPLD interrupt */ + + CPLD_INTERRUPTS = 0x0c; /* Disable all CPLD interrupts */ + GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */ + GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */ + GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */ + barrier (); + GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */ + + /* Cascade CPLD interrupts */ + + for (irq = IRQ_BOARD_START; + irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { + set_irq_chip (irq, &lh7a40x_cpld_chip); + set_irq_handler (irq, do_edge_IRQ); + set_irq_flags (irq, IRQF_VALID); + } + + set_irq_chained_handler ((cpld_version == 0x28) + ? IRQ_CPLD_V28 + : IRQ_CPLD_V34, + lh7a40x_cpld_handler); +} -- cgit v1.2.3-55-g7522