From 2e12bd7ef175c9dc55dc215823b62a2247865012 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 28 May 2009 14:03:59 -0700 Subject: ARM: OMAP3: SDRC: add timing data for Micron MT46H32M32LF-6, v2 Add timing data for the Micron MT46H32M32LF-6 SDRAM chip, used on the OMAP3 Beagle and EVM boards. Original timing data is from the Micron datasheet PDF downloaded from: http://download.micron.com/pdf/datasheets/dram/mobile/1gb_ddr_mobile_sdram_t48m.pdf Thanks to Rajendra Nayak for his help identifying the chips used on Beagle & OMAP3EVM. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h (limited to 'arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h') diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h new file mode 100644 index 000000000000..02e1c2d4705f --- /dev/null +++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h @@ -0,0 +1,55 @@ +/* + * SDRC register values for the Micron MT46H32M32LF-6 + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2009 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF +#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF + +#include + +/* Micron MT46H32M32LF-6 */ +/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */ +static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = { + [0] = { + .rate = 166000000, + .actim_ctrla = 0x9a9db4c6, + .actim_ctrlb = 0x00011217, + .rfr_ctrl = 0x0004dc01, + .mr = 0x00000032, + }, + [1] = { + .rate = 165941176, + .actim_ctrla = 0x9a9db4c6, + .actim_ctrlb = 0x00011217, + .rfr_ctrl = 0x0004dc01, + .mr = 0x00000032, + }, + [2] = { + .rate = 83000000, + .actim_ctrla = 0x51512283, + .actim_ctrlb = 0x0001120c, + .rfr_ctrl = 0x00025501, + .mr = 0x00000032, + }, + [3] = { + .rate = 82970588, + .actim_ctrla = 0x51512283, + .actim_ctrlb = 0x0001120c, + .rfr_ctrl = 0x00025501, + .mr = 0x00000032, + }, + [4] = { + .rate = 0 + }, +}; + +#endif -- cgit v1.2.3-55-g7522