From 76d500182061dcc7508e6b829af097348fa7d804 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Fri, 4 Mar 2011 15:33:55 +0000 Subject: ARM: omap3: Remove hand-encoded SMC instructions For various reasons, Linux now only officially supports being built with tools which are new enough to understand the SMC instruction. Replacing the hand-encoded instructions when the mnemonic also allows for correct assembly in Thumb-2 (otherwise, the result is random data in the middle of the code). The Makefile already ensures that this file is built with a high enough gcc -march= flag (armv7-a). Signed-off-by: Dave Martin Tested-by: Santosh Shilimkar Tested-by: Jean Pihet Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 98d8232808b8..a05c348885ac 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -133,7 +133,7 @@ ENTRY(save_secure_ram_context) mov r6, #0xff mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) nop nop nop @@ -408,7 +408,7 @@ skipl2dis: adr r3, l2_inv_api_params @ r3 points to dummy parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) /* Write to Aux control register to set some bits */ mov r0, #42 @ set service ID for PPA mov r12, r0 @ copy secure Service ID in r12 @@ -419,7 +419,7 @@ skipl2dis: ldr r3, [r4, #0xBC] @ r3 points to parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE /* Restore L2 aux control register */ @@ -434,7 +434,7 @@ skipl2dis: adds r3, r3, #8 @ r3 points to parameters mcr p15, 0, r0, c7, c10, 4 @ data write barrier mcr p15, 0, r0, c7, c10, 5 @ data memory barrier - .word 0xE1600071 @ call SMI monitor (smi #1) + smc #1 @ call SMI monitor (smi #1) #endif b logic_l1_restore @@ -443,18 +443,18 @@ l2_inv_api_params: l2_inv_gp: /* Execute smi to invalidate L2 cache */ mov r12, #0x1 @ set up to invalidate L2 - .word 0xE1600070 @ Call SMI monitor (smieq) + smc #0 @ Call SMI monitor (smieq) /* Write to Aux control register to set some bits */ ldr r4, scratchpad_base ldr r3, [r4,#0xBC] ldr r0, [r3,#4] mov r12, #0x3 - .word 0xE1600070 @ Call SMI monitor (smieq) + smc #0 @ Call SMI monitor (smieq) ldr r4, scratchpad_base ldr r3, [r4,#0xBC] ldr r0, [r3,#12] mov r12, #0x2 - .word 0xE1600070 @ Call SMI monitor (smieq) + smc #0 @ Call SMI monitor (smieq) logic_l1_restore: ldr r1, l2dis_3630 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630 -- cgit v1.2.3-55-g7522 From dd31394779aa288eb6b9c42672ffcb6d05d6c414 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Fri, 4 Mar 2011 15:33:57 +0000 Subject: ARM: omap3: Thumb-2 compatibility for sleep34xx.S * Build unconditionally as ARM for correct interoperation with OMAP firmware. * Fix an out-of-range ADR when building for ARM. * Remove deprecated PC-relative stores. * Add the required ENDPROC() directive for each ENTRY(). * .align before data words. * Handle non-interworking return from v7_flush_dcache_all. Signed-off-by: Dave Martin Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 48 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 5 deletions(-) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index a05c348885ac..0c1b33511fed 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -64,6 +64,11 @@ #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) +/* + * This file needs be built unconditionally as ARM to interoperate correctly + * with non-Thumb-2-capable firmware. + */ + .arm /* * API functions @@ -82,6 +87,8 @@ ENTRY(get_restore_pointer) stmfd sp!, {lr} @ save registers on stack adr r0, restore ldmfd sp!, {pc} @ restore regs and return +ENDPROC(get_restore_pointer) + .align ENTRY(get_restore_pointer_sz) .word . - get_restore_pointer @@ -91,6 +98,8 @@ ENTRY(get_omap3630_restore_pointer) stmfd sp!, {lr} @ save registers on stack adr r0, restore_3630 ldmfd sp!, {pc} @ restore regs and return +ENDPROC(get_omap3630_restore_pointer) + .align ENTRY(get_omap3630_restore_pointer_sz) .word . - get_omap3630_restore_pointer @@ -100,6 +109,8 @@ ENTRY(get_es3_restore_pointer) stmfd sp!, {lr} @ save registers on stack adr r0, restore_es3 ldmfd sp!, {pc} @ restore regs and return +ENDPROC(get_es3_restore_pointer) + .align ENTRY(get_es3_restore_pointer_sz) .word . - get_es3_restore_pointer @@ -113,8 +124,10 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) stmfd sp!, {lr} @ save registers on stack /* Setup so that we will disable and enable l2 */ mov r1, #0x1 - str r1, l2dis_3630 + adrl r2, l2dis_3630 @ may be too distant for plain adr + str r1, [r2] ldmfd sp!, {pc} @ restore regs and return +ENDPROC(enable_omap3630_toggle_l2_on_restore) .text /* Function to call rom code to save secure ram context */ @@ -139,12 +152,14 @@ ENTRY(save_secure_ram_context) nop nop ldmfd sp!, {r1-r12, pc} + .align sram_phy_addr_mask: .word SRAM_BASE_P high_mask: .word 0xffff api_params: .word 0x4, 0x0, 0x0, 0x1, 0x1 +ENDPROC(save_secure_ram_context) ENTRY(save_secure_ram_context_sz) .word . - save_secure_ram_context @@ -279,8 +294,18 @@ clean_l2: * - 'might' have to copy address, load and jump to it */ ldr r1, kernel_flush - mov lr, pc - bx r1 + blx r1 + /* + * The kernel doesn't interwork: v7_flush_dcache_all in particluar will + * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. + * This sequence switches back to ARM. Note that .align may insert a + * nop: bx pc needs to be word-aligned in order to work. + */ + THUMB( .thumb ) + THUMB( .align ) + THUMB( bx pc ) + THUMB( nop ) + .arm omap3_do_wfi: ldr r4, sdrc_power @ read the SDRC_POWER register @@ -438,6 +463,7 @@ skipl2dis: #endif b logic_l1_restore + .align l2_inv_api_params: .word 0x1, 0x00 l2_inv_gp: @@ -607,6 +633,7 @@ usettbr0: /* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */ .text + .align 3 ENTRY(es3_sdrc_fix) ldr r4, sdrc_syscfg @ get config addr ldr r5, [r4] @ get value @@ -634,6 +661,7 @@ ENTRY(es3_sdrc_fix) str r5, [r4] @ kick off refreshes bx lr + .align sdrc_syscfg: .word SDRC_SYSCONFIG_P sdrc_mr_0: @@ -648,6 +676,7 @@ sdrc_emr2_1: .word SDRC_EMR2_1_P sdrc_manual_1: .word SDRC_MANUAL_1_P +ENDPROC(es3_sdrc_fix) ENTRY(es3_sdrc_fix_sz) .word . - es3_sdrc_fix @@ -682,6 +711,12 @@ wait_sdrc_ready: bic r5, r5, #0x40 str r5, [r4] +/* + * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a + * base instead. + * Be careful not to clobber r7 when maintaing this code. + */ + is_dll_in_lock_mode: /* Is dll in lock mode? */ ldr r4, sdrc_dlla_ctrl @@ -689,10 +724,11 @@ is_dll_in_lock_mode: tst r5, #0x4 bxne lr @ Return if locked /* wait till dll locks */ + adr r7, kick_counter wait_dll_lock_timed: ldr r4, wait_dll_lock_counter add r4, r4, #1 - str r4, wait_dll_lock_counter + str r4, [r7, #wait_dll_lock_counter - kick_counter] ldr r4, sdrc_dlla_status /* Wait 20uS for lock */ mov r6, #8 @@ -718,9 +754,10 @@ kick_dll: dsb ldr r4, kick_counter add r4, r4, #1 - str r4, kick_counter + str r4, [r7] @ kick_counter b wait_dll_lock_timed + .align cm_idlest1_core: .word CM_IDLEST1_CORE_V cm_idlest_ckgen: @@ -763,6 +800,7 @@ kick_counter: .word 0 wait_dll_lock_counter: .word 0 +ENDPROC(omap34xx_cpu_suspend) ENTRY(omap34xx_cpu_suspend_sz) .word . - omap34xx_cpu_suspend -- cgit v1.2.3-55-g7522 From 4444d712fd5b31f2348b57eaa2bbdc5e68c4e1b6 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sun, 23 Jan 2011 19:00:34 +0530 Subject: OMAP3: PM: Use ARMv7 supported instructions instead of legacy CP15 ones On ARMv7 dsb, dmb instructions are supported and can be used directly instead of their cp15 equivalnet. Also remove the opcodes for smc and use the available instruction directly in OMAP3 low power asm code Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 0c1b33511fed..1c17ee81cb12 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -144,8 +144,8 @@ ENTRY(save_secure_ram_context) mov r1, #0 @ set task id for ROM code in r1 mov r2, #4 @ set some flags in r2, r6 mov r6, #0xff - mcr p15, 0, r0, c7, c10, 4 @ data write barrier - mcr p15, 0, r0, c7, c10, 5 @ data memory barrier + dsb @ data write barrier + dmb @ data memory barrier smc #1 @ call SMI monitor (smi #1) nop nop @@ -314,9 +314,8 @@ omap3_do_wfi: str r5, [r4] @ write back to SDRC_POWER register /* Data memory barrier and Data sync barrier */ - mov r1, #0 - mcr p15, 0, r1, c7, c10, 4 - mcr p15, 0, r1, c7, c10, 5 + dsb + dmb /* * =================================== @@ -431,8 +430,8 @@ skipl2dis: mov r2, #4 @ set some flags in r2, r6 mov r6, #0xff adr r3, l2_inv_api_params @ r3 points to dummy parameters - mcr p15, 0, r0, c7, c10, 4 @ data write barrier - mcr p15, 0, r0, c7, c10, 5 @ data memory barrier + dsb @ data write barrier + dmb @ data memory barrier smc #1 @ call SMI monitor (smi #1) /* Write to Aux control register to set some bits */ mov r0, #42 @ set service ID for PPA @@ -442,8 +441,8 @@ skipl2dis: mov r6, #0xff ldr r4, scratchpad_base ldr r3, [r4, #0xBC] @ r3 points to parameters - mcr p15, 0, r0, c7, c10, 4 @ data write barrier - mcr p15, 0, r0, c7, c10, 5 @ data memory barrier + dsb @ data write barrier + dmb @ data memory barrier smc #1 @ call SMI monitor (smi #1) #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE @@ -457,8 +456,8 @@ skipl2dis: ldr r4, scratchpad_base ldr r3, [r4, #0xBC] adds r3, r3, #8 @ r3 points to parameters - mcr p15, 0, r0, c7, c10, 4 @ data write barrier - mcr p15, 0, r0, c7, c10, 5 @ data memory barrier + dsb @ data write barrier + dmb @ data memory barrier smc #1 @ call SMI monitor (smi #1) #endif b logic_l1_restore -- cgit v1.2.3-55-g7522 From 8409d57bc342536ffe96acc7cd6c7575d98d3edb Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sun, 23 Jan 2011 16:04:39 +0530 Subject: OMAP3: PM: Fix the MMU on sequence in the asm code Add necessary barriers after enabling MMU. Also use the sane way to load pc and jump to it instead of executing ldma first up. Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 1c17ee81cb12..a31845a201e9 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -617,12 +617,17 @@ usettbr0: ldr r2, cache_pred_disable_mask and r4, r2 mcr p15, 0, r4, c1, c0, 0 + dsb + isb + ldr r0, =restoremmu_on + bx r0 /* * ============================== * == Exit point from OFF mode == * ============================== */ +restoremmu_on: ldmfd sp!, {r0-r12, pc} @ restore regs and return -- cgit v1.2.3-55-g7522 From c9749a352383d4d2d25eb28062afd1a7eee115b7 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sun, 23 Jan 2011 19:33:53 +0530 Subject: OMAP3: PM: Allow the cache clean when L1 is lost. When L1 cache is suppose to be lost, it needs to be cleaned before entrering to the low power mode. While at this, also fix few comments and remove un-necessary clean_l2 lable. Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index a31845a201e9..f75a166f0a21 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -188,12 +188,12 @@ ENTRY(omap34xx_cpu_suspend) stmfd sp!, {r0-r12, lr} @ save registers on stack /* - * r0 contains restore pointer in sdram + * r0 contains CPU context save/restore pointer in sdram * r1 contains information about saving context: * 0 - No context lost * 1 - Only L1 and logic lost - * 2 - Only L2 lost - * 3 - Both L1 and L2 lost + * 2 - Only L2 lost (Even L1 is retained we clean it along with L2) + * 3 - Both L1 and L2 lost and logic lost */ /* Directly jump to WFI is the context save is not required */ @@ -277,15 +277,6 @@ l1_logic_lost: stmia r8!, {r4} clean_caches: - /* - * Clean Data or unified cache to POU - * How to invalidate only L1 cache???? - #FIX_ME# - * mcr p15, 0, r11, c7, c11, 1 - */ - cmp r1, #0x1 @ Check whether L2 inval is required - beq omap3_do_wfi - -clean_l2: /* * jump out to kernel flush routine * - reuse that code is better -- cgit v1.2.3-55-g7522 From 46f557cb453b9f3b6dc36b8179c2c36932a2ea64 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sun, 23 Jan 2011 21:37:03 +0530 Subject: OMAP3: PM: Remove un-necessary cp15 registers form low power cpu context The current code saves few un-necessary registers which are read-only or write-only, unused CP15 registers. Remove them and keep only necessary CP15 registers part of low power context save/restore. Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 156 +++++++++++----------------------------- 1 file changed, 40 insertions(+), 116 deletions(-) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index f75a166f0a21..99e43cc5a503 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -214,66 +214,29 @@ save_context_wfi: beq clean_caches l1_logic_lost: - /* Store sp and spsr to SDRAM */ - mov r4, sp - mrs r5, spsr - mov r6, lr + mov r4, sp @ Store sp + mrs r5, spsr @ Store spsr + mov r6, lr @ Store lr stmia r8!, {r4-r6} - /* Save all ARM registers */ - /* Coprocessor access control register */ - mrc p15, 0, r6, c1, c0, 2 - stmia r8!, {r6} - /* TTBR0, TTBR1 and Translation table base control */ - mrc p15, 0, r4, c2, c0, 0 - mrc p15, 0, r5, c2, c0, 1 - mrc p15, 0, r6, c2, c0, 2 - stmia r8!, {r4-r6} - /* - * Domain access control register, data fault status register, - * and instruction fault status register - */ - mrc p15, 0, r4, c3, c0, 0 - mrc p15, 0, r5, c5, c0, 0 - mrc p15, 0, r6, c5, c0, 1 - stmia r8!, {r4-r6} - /* - * Data aux fault status register, instruction aux fault status, - * data fault address register and instruction fault address register - */ - mrc p15, 0, r4, c5, c1, 0 - mrc p15, 0, r5, c5, c1, 1 - mrc p15, 0, r6, c6, c0, 0 - mrc p15, 0, r7, c6, c0, 2 - stmia r8!, {r4-r7} - /* - * user r/w thread and process ID, user r/o thread and process ID, - * priv only thread and process ID, cache size selection - */ - mrc p15, 0, r4, c13, c0, 2 - mrc p15, 0, r5, c13, c0, 3 - mrc p15, 0, r6, c13, c0, 4 - mrc p15, 2, r7, c0, c0, 0 + + mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register + mrc p15, 0, r5, c2, c0, 0 @ TTBR0 + mrc p15, 0, r6, c2, c0, 1 @ TTBR1 + mrc p15, 0, r7, c2, c0, 2 @ TTBCR stmia r8!, {r4-r7} - /* Data TLB lockdown, instruction TLB lockdown registers */ - mrc p15, 0, r5, c10, c0, 0 - mrc p15, 0, r6, c10, c0, 1 - stmia r8!, {r5-r6} - /* Secure or non secure vector base address, FCSE PID, Context PID*/ - mrc p15, 0, r4, c12, c0, 0 - mrc p15, 0, r5, c13, c0, 0 - mrc p15, 0, r6, c13, c0, 1 - stmia r8!, {r4-r6} - /* Primary remap, normal remap registers */ - mrc p15, 0, r4, c10, c2, 0 - mrc p15, 0, r5, c10, c2, 1 - stmia r8!,{r4-r5} - /* Store current cpsr*/ - mrs r2, cpsr - stmia r8!, {r2} + mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register + mrc p15, 0, r5, c10, c2, 0 @ PRRR + mrc p15, 0, r6, c10, c2, 1 @ NMRR + stmia r8!,{r4-r6} + + mrc p15, 0, r4, c13, c0, 1 @ Context ID + mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID + mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address + mrs r7, cpsr @ Store current cpsr + stmia r8!, {r4-r7} - mrc p15, 0, r4, c1, c0, 0 - /* save control register */ + mrc p15, 0, r4, c1, c0, 0 @ save control register stmia r8!, {r4} clean_caches: @@ -489,68 +452,29 @@ skipl2reen: ldr r4, scratchpad_base ldr r3, [r4,#0xBC] adds r3, r3, #16 + ldmia r3!, {r4-r6} - mov sp, r4 - msr spsr_cxsf, r5 - mov lr, r6 - - ldmia r3!, {r4-r9} - /* Coprocessor access Control Register */ - mcr p15, 0, r4, c1, c0, 2 - - /* TTBR0 */ - MCR p15, 0, r5, c2, c0, 0 - /* TTBR1 */ - MCR p15, 0, r6, c2, c0, 1 - /* Translation table base control register */ - MCR p15, 0, r7, c2, c0, 2 - /* Domain access Control Register */ - MCR p15, 0, r8, c3, c0, 0 - /* Data fault status Register */ - MCR p15, 0, r9, c5, c0, 0 - - ldmia r3!,{r4-r8} - /* Instruction fault status Register */ - MCR p15, 0, r4, c5, c0, 1 - /* Data Auxiliary Fault Status Register */ - MCR p15, 0, r5, c5, c1, 0 - /* Instruction Auxiliary Fault Status Register*/ - MCR p15, 0, r6, c5, c1, 1 - /* Data Fault Address Register */ - MCR p15, 0, r7, c6, c0, 0 - /* Instruction Fault Address Register*/ - MCR p15, 0, r8, c6, c0, 2 - ldmia r3!,{r4-r7} + mov sp, r4 @ Restore sp + msr spsr_cxsf, r5 @ Restore spsr + mov lr, r6 @ Restore lr - /* User r/w thread and process ID */ - MCR p15, 0, r4, c13, c0, 2 - /* User ro thread and process ID */ - MCR p15, 0, r5, c13, c0, 3 - /* Privileged only thread and process ID */ - MCR p15, 0, r6, c13, c0, 4 - /* Cache size selection */ - MCR p15, 2, r7, c0, c0, 0 - ldmia r3!,{r4-r8} - /* Data TLB lockdown registers */ - MCR p15, 0, r4, c10, c0, 0 - /* Instruction TLB lockdown registers */ - MCR p15, 0, r5, c10, c0, 1 - /* Secure or Nonsecure Vector Base Address */ - MCR p15, 0, r6, c12, c0, 0 - /* FCSE PID */ - MCR p15, 0, r7, c13, c0, 0 - /* Context PID */ - MCR p15, 0, r8, c13, c0, 1 - - ldmia r3!,{r4-r5} - /* Primary memory remap register */ - MCR p15, 0, r4, c10, c2, 0 - /* Normal memory remap register */ - MCR p15, 0, r5, c10, c2, 1 - - /* Restore cpsr */ - ldmia r3!,{r4} @ load CPSR from SDRAM - msr cpsr, r4 @ store cpsr + ldmia r3!, {r4-r7} + mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register + mcr p15, 0, r5, c2, c0, 0 @ TTBR0 + mcr p15, 0, r6, c2, c0, 1 @ TTBR1 + mcr p15, 0, r7, c2, c0, 2 @ TTBCR + + ldmia r3!,{r4-r6} + mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register + mcr p15, 0, r5, c10, c2, 0 @ PRRR + mcr p15, 0, r6, c10, c2, 1 @ NMRR + + + ldmia r3!,{r4-r7} + mcr p15, 0, r4, c13, c0, 1 @ Context ID + mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID + mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address + msr cpsr, r7 @ store cpsr /* Enabling MMU here */ mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl -- cgit v1.2.3-55-g7522 From 9062511097683b4422f023d181b4a8b2db1a7a72 Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Sun, 23 Jan 2011 22:51:09 +0530 Subject: OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation On the newer ARM processors like CortexA8, CortexA9, the caches can be speculatively loaded while they are getting flushed. Clear the SCTLR C bit to prevent further data cache allocation as part of cache clean routine Signed-off-by: Santosh Shilimkar Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/sleep34xx.S | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm/mach-omap2/sleep34xx.S') diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 99e43cc5a503..e60ac1f71bd4 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -246,6 +246,27 @@ clean_caches: * - it executes in a cached space so is faster than refetch per-block * - should be faster and will change with kernel * - 'might' have to copy address, load and jump to it + * Flush all data from the L1 data cache before disabling + * SCTLR.C bit. + */ + ldr r1, kernel_flush + mov lr, pc + bx r1 + + /* + * Clear the SCTLR.C bit to prevent further data cache + * allocation. Clearing SCTLR.C would make all the data accesses + * strongly ordered and would not hit the cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(1 << 2) @ Disable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + /* + * Invalidate L1 data cache. Even though only invalidate is + * necessary exported flush API is used here. Doing clean + * on already clean cache would be almost NOP. */ ldr r1, kernel_flush blx r1 @@ -295,6 +316,12 @@ omap3_do_wfi: nop bl wait_sdrc_ok + mrc p15, 0, r0, c1, c0, 0 + tst r0, #(1 << 2) @ Check C bit enabled? + orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared + mcreq p15, 0, r0, c1, c0, 0 + isb + /* * =================================== * == Exit point from non-OFF modes == -- cgit v1.2.3-55-g7522