From 2332656aec7ae88248cbd9aa6b35c857bb449c94 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:17 +0200 Subject: arm: mach-orion5x: use plus instead of or for address definitions Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-orion5x/include/mach/bridge-regs.h | 20 ++++----- arch/arm/mach-orion5x/include/mach/orion5x.h | 52 ++++++++++++------------ arch/arm/mach-orion5x/pci.c | 2 +- 3 files changed, 37 insertions(+), 37 deletions(-) (limited to 'arch/arm/mach-orion5x') diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h index 11a3c1e9801f..461fd69a10ae 100644 --- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -13,27 +13,27 @@ #include -#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) -#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) -#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) #define WDT_RESET_OUT_EN 0x0002 -#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) -#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) -#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) #define WDT_INT_REQ 0x0008 #define BRIDGE_INT_TIMER1_CLR (~0x0004) -#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) -#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) -#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) -#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300) +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) +#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) #endif diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 683e085ce162..87bd378b8203 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -68,42 +68,42 @@ * Orion Registers Map ******************************************************************************/ -#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) -#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) -#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) -#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) -#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) +#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000) +#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500) +#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000) +#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000) +#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x)) #define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) -#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) -#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) -#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) -#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) -#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) -#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) +#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600) +#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000) +#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100) -#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) -#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x20000) +#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) +#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000) -#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) +#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000) -#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) +#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000) -#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) -#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) +#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000) +#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000) -#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) -#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) +#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900) +#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900) -#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) -#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) +#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000) +#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000) -#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) -#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) +#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000) +#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000) -#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) +#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000) -#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) -#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) +#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000) +#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000) /******************************************************************************* * Device Bus Registers diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index cb19e1661bb3..b36f928d017c 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -198,7 +198,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) /***************************************************************************** * PCI controller ****************************************************************************/ -#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) +#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x)) #define PCI_MODE ORION5X_PCI_REG(0xd00) #define PCI_CMD ORION5X_PCI_REG(0xc00) #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) -- cgit v1.2.3-55-g7522 From 3904a39321422d424f790d18a4746b99e1aed0e9 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:21 +0200 Subject: arm: mach-orion5x: use IOMEM() for base address definitions We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-orion5x code. Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-orion5x/addr-map.c | 2 +- arch/arm/mach-orion5x/common.c | 19 +++++++++++-------- arch/arm/mach-orion5x/dns323-setup.c | 2 +- arch/arm/mach-orion5x/include/mach/orion5x.h | 8 ++++---- arch/arm/mach-orion5x/irq.c | 5 +++-- arch/arm/mach-orion5x/mpp.c | 3 ++- arch/arm/mach-orion5x/pci.c | 4 ++-- 7 files changed, 24 insertions(+), 19 deletions(-) (limited to 'arch/arm/mach-orion5x') diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index eaac83d1df6f..d309f53b7a0c 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, static struct orion_addr_map_cfg addr_map_cfg __initdata = { .num_wins = 8, .cpu_win_can_remap = cpu_win_can_remap, - .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, + .bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 410291c67666..a890cb0eb83d 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -42,22 +42,22 @@ ****************************************************************************/ static struct map_desc orion5x_io_desc[] __initdata = { { - .virtual = ORION5X_REGS_VIRT_BASE, + .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), .length = ORION5X_REGS_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_IO_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCIE_IO_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), .length = ORION5X_PCIE_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCI_IO_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCI_IO_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), .length = ORION5X_PCI_IO_SIZE, .type = MT_DEVICE, }, { - .virtual = ORION5X_PCIE_WA_VIRT_BASE, + .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE, .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), .length = ORION5X_PCIE_WA_SIZE, .type = MT_DEVICE, @@ -156,7 +156,8 @@ void __init orion5x_spi_init() ****************************************************************************/ void __init orion5x_uart0_init(void) { - orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, + orion_uart0_init((unsigned long) UART0_VIRT_BASE, + UART0_PHYS_BASE, IRQ_ORION5X_UART0, tclk); } @@ -165,7 +166,8 @@ void __init orion5x_uart0_init(void) ****************************************************************************/ void __init orion5x_uart1_init(void) { - orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, + orion_uart1_init((unsigned long) UART1_VIRT_BASE, + UART1_PHYS_BASE, IRQ_ORION5X_UART1, tclk); } @@ -203,7 +205,7 @@ void __init orion5x_wdt_init(void) ****************************************************************************/ void __init orion5x_init_early(void) { - orion_time_set_base(TIMER_VIRT_BASE); + orion_time_set_base((unsigned long) TIMER_VIRT_BASE); } int orion5x_tclk; @@ -224,7 +226,8 @@ static void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); - orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, + orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE, + BRIDGE_INT_TIMER1_CLR, IRQ_ORION5X_BRIDGE, orion5x_tclk); } diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index d470864b4e42..3a5e6fc197f7 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -700,7 +700,7 @@ static void __init dns323_init(void) * Note: AFAIK, rev B1 needs the same treatement but I'll let * somebody else test it. */ - writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c); + writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c); break; } } diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 87bd378b8203..6fd38ab5e267 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -37,16 +37,16 @@ * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) ****************************************************************************/ #define ORION5X_REGS_PHYS_BASE 0xf1000000 -#define ORION5X_REGS_VIRT_BASE 0xfdd00000 +#define ORION5X_REGS_VIRT_BASE IOMEM(0xfdd00000) #define ORION5X_REGS_SIZE SZ_1M #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 -#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000 +#define ORION5X_PCIE_IO_VIRT_BASE IOMEM(0xfde00000) #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 #define ORION5X_PCIE_IO_SIZE SZ_1M #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 -#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000 +#define ORION5X_PCI_IO_VIRT_BASE IOMEM(0xfdf00000) #define ORION5X_PCI_IO_BUS_BASE 0x00100000 #define ORION5X_PCI_IO_SIZE SZ_1M @@ -55,7 +55,7 @@ /* Relevant only for Orion-1/Orion-NAS */ #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 -#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000 +#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfe000000) #define ORION5X_PCIE_WA_SIZE SZ_16M #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 17da7091d310..bf9ff4f00818 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -24,11 +25,11 @@ static int __initdata gpio0_irqs[4] = { void __init orion5x_init_irq(void) { - orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); + orion_irq_init(0, MAIN_IRQ_MASK); /* * Initialize gpiolib for GPIOs 0-31. */ - orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0, + orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 5b70026f478c..30f5ef6e2ec2 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -40,5 +40,6 @@ static unsigned int __init orion5x_variant(void) void __init orion5x_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, orion5x_variant(), - MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE); + MPP_MAX, + (unsigned long) ORION5X_DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index b36f928d017c..b0822a864e0f 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -38,7 +38,7 @@ /***************************************************************************** * PCIe controller ****************************************************************************/ -#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) +#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE) void __init orion5x_pcie_id(u32 *dev, u32 *rev) { @@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, + ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE, bus, devfn, where, size, val); return ret; -- cgit v1.2.3-55-g7522 From d19beac1d9358bb4a2a303f4327bf2d40ba88464 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:23 +0200 Subject: arm: plat-orion: use void __iomem pointers for UART registration functions The registration functions for UARTs now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 12 ++++-------- arch/arm/mach-kirkwood/common.c | 6 ++---- arch/arm/mach-mv78xx0/common.c | 12 ++++-------- arch/arm/mach-orion5x/common.c | 6 ++---- arch/arm/plat-orion/common.c | 12 ++++++------ arch/arm/plat-orion/include/plat/common.h | 8 ++++---- 6 files changed, 22 insertions(+), 34 deletions(-) (limited to 'arch/arm/mach-orion5x') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 533fd8123c70..ba55f631cccc 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -128,8 +128,7 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init dove_uart0_init(void) { - orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE, - DOVE_UART0_PHYS_BASE, + orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE, IRQ_DOVE_UART_0, tclk); } @@ -138,8 +137,7 @@ void __init dove_uart0_init(void) ****************************************************************************/ void __init dove_uart1_init(void) { - orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE, - DOVE_UART1_PHYS_BASE, + orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE, IRQ_DOVE_UART_1, tclk); } @@ -148,8 +146,7 @@ void __init dove_uart1_init(void) ****************************************************************************/ void __init dove_uart2_init(void) { - orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE, - DOVE_UART2_PHYS_BASE, + orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE, IRQ_DOVE_UART_2, tclk); } @@ -158,8 +155,7 @@ void __init dove_uart2_init(void) ****************************************************************************/ void __init dove_uart3_init(void) { - orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE, - DOVE_UART3_PHYS_BASE, + orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE, IRQ_DOVE_UART_3, tclk); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 75bc04da8d99..defceca51841 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -456,8 +456,7 @@ void __init kirkwood_i2c_init(void) void __init kirkwood_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_KIRKWOOD_UART_0, tclk); } @@ -467,8 +466,7 @@ void __init kirkwood_uart0_init(void) ****************************************************************************/ void __init kirkwood_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_KIRKWOOD_UART_1, tclk); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index c4e3458e0674..fcda4a4f830d 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -300,8 +300,7 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) ****************************************************************************/ void __init mv78xx0_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_MV78XX0_UART_0, tclk); } @@ -311,8 +310,7 @@ void __init mv78xx0_uart0_init(void) ****************************************************************************/ void __init mv78xx0_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_MV78XX0_UART_1, tclk); } @@ -322,8 +320,7 @@ void __init mv78xx0_uart1_init(void) ****************************************************************************/ void __init mv78xx0_uart2_init(void) { - orion_uart2_init((unsigned long) UART2_VIRT_BASE, - UART2_PHYS_BASE, + orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE, IRQ_MV78XX0_UART_2, tclk); } @@ -332,8 +329,7 @@ void __init mv78xx0_uart2_init(void) ****************************************************************************/ void __init mv78xx0_uart3_init(void) { - orion_uart3_init((unsigned long) UART3_VIRT_BASE, - UART3_PHYS_BASE, + orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE, IRQ_MV78XX0_UART_3, tclk); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index a890cb0eb83d..79f9ffb9a142 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -156,8 +156,7 @@ void __init orion5x_spi_init() ****************************************************************************/ void __init orion5x_uart0_init(void) { - orion_uart0_init((unsigned long) UART0_VIRT_BASE, - UART0_PHYS_BASE, + orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE, IRQ_ORION5X_UART0, tclk); } @@ -166,8 +165,7 @@ void __init orion5x_uart0_init(void) ****************************************************************************/ void __init orion5x_uart1_init(void) { - orion_uart1_init((unsigned long) UART1_VIRT_BASE, - UART1_PHYS_BASE, + orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE, IRQ_ORION5X_UART1, tclk); } diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index b8b747a9d360..5bed71139945 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -86,13 +86,13 @@ static void __init uart_complete( struct platform_device *orion_uart, struct plat_serial8250_port *data, struct resource *resources, - unsigned int membase, + void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) { data->mapbase = mapbase; - data->membase = (void __iomem *)membase; + data->membase = membase; data->irq = irq; data->uartclk = uart_get_clk_rate(clk); orion_uart->dev.platform_data = data; @@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = { .id = PLAT8250_DEV_PLATFORM, }; -void __init orion_uart0_init(unsigned int membase, +void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = { .id = PLAT8250_DEV_PLATFORM1, }; -void __init orion_uart1_init(unsigned int membase, +void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = { .id = PLAT8250_DEV_PLATFORM2, }; -void __init orion_uart2_init(unsigned int membase, +void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) @@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = { .id = 3, }; -void __init orion_uart3_init(unsigned int membase, +void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk) diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index ae2377ef63e5..6bbc3fe5f58e 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -13,22 +13,22 @@ struct dsa_platform_data; -void __init orion_uart0_init(unsigned int membase, +void __init orion_uart0_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart1_init(unsigned int membase, +void __init orion_uart1_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart2_init(unsigned int membase, +void __init orion_uart2_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -void __init orion_uart3_init(unsigned int membase, +void __init orion_uart3_init(void __iomem *membase, resource_size_t mapbase, unsigned int irq, struct clk *clk); -- cgit v1.2.3-55-g7522 From 5a2f55019391218d8c08c6f9d32591d91200de77 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:24 +0200 Subject: arm: plat-orion: use void __iomem pointers for MPP functions The registration function for MPP now takes void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/mpp.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/mpp.c | 3 +-- arch/arm/mach-kirkwood/mpp.c | 3 +-- arch/arm/mach-mv78xx0/mpp.c | 3 +-- arch/arm/mach-orion5x/mpp.c | 3 +-- arch/arm/plat-orion/include/plat/mpp.h | 2 +- arch/arm/plat-orion/mpp.c | 6 +++--- 6 files changed, 8 insertions(+), 12 deletions(-) (limited to 'arch/arm/mach-orion5x') diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index fc04ebefbebd..7f70afc26f91 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c @@ -151,8 +151,7 @@ void __init dove_mpp_conf(unsigned int *mpp_list, dove_mpp_dump_regs(); /* Use platform code for pins 0-23 */ - orion_mpp_conf(mpp_list, 0, MPP_MAX, - (unsigned long) DOVE_MPP_VIRT_BASE); + orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE); dove_mpp_conf_grp(mpp_grp_list); dove_mpp_cfg_au1(grp_au1_52_57); diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c index 67742793f3c4..0c6ad63f10c7 100644 --- a/arch/arm/mach-kirkwood/mpp.c +++ b/arch/arm/mach-kirkwood/mpp.c @@ -38,6 +38,5 @@ static unsigned int __init kirkwood_variant(void) void __init kirkwood_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, kirkwood_variant(), - MPP_MAX, - (unsigned long) DEV_BUS_VIRT_BASE); + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index 4da82f85d1ce..df50342179e2 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -33,6 +33,5 @@ static unsigned int __init mv78xx0_variant(void) void __init mv78xx0_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, mv78xx0_variant(), - MPP_MAX, - (unsigned long) DEV_BUS_VIRT_BASE); + MPP_MAX, DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c index 30f5ef6e2ec2..5b70026f478c 100644 --- a/arch/arm/mach-orion5x/mpp.c +++ b/arch/arm/mach-orion5x/mpp.c @@ -40,6 +40,5 @@ static unsigned int __init orion5x_variant(void) void __init orion5x_mpp_conf(unsigned int *mpp_list) { orion_mpp_conf(mpp_list, orion5x_variant(), - MPP_MAX, - (unsigned long) ORION5X_DEV_BUS_VIRT_BASE); + MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE); } diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h index 723adce99f41..254552fee889 100644 --- a/arch/arm/plat-orion/include/plat/mpp.h +++ b/arch/arm/plat-orion/include/plat/mpp.h @@ -29,6 +29,6 @@ #define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1) void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, - unsigned int mpp_max, unsigned int dev_bus); + unsigned int mpp_max, void __iomem *dev_bus); #endif diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c index 3b1e17bd3d17..20d4208436c8 100644 --- a/arch/arm/plat-orion/mpp.c +++ b/arch/arm/plat-orion/mpp.c @@ -17,15 +17,15 @@ #include /* Address of the ith MPP control register */ -static __init unsigned long mpp_ctrl_addr(unsigned int i, - unsigned long dev_bus) +static __init void __iomem *mpp_ctrl_addr(unsigned int i, + void __iomem *dev_bus) { return dev_bus + (i) * 4; } void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, - unsigned int mpp_max, unsigned int dev_bus) + unsigned int mpp_max, void __iomem *dev_bus) { unsigned int mpp_nr_regs = (1 + mpp_max/8); u32 mpp_ctrl[mpp_nr_regs]; -- cgit v1.2.3-55-g7522 From e96a0309f8545d539c1bf4acd5b58727a8f39818 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:25 +0200 Subject: arm: plat-orion: use void __iomem pointers for time functions The functions for time management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/common.c | 5 ++--- arch/arm/mach-kirkwood/common.c | 5 ++--- arch/arm/mach-mv78xx0/common.c | 5 ++--- arch/arm/mach-orion5x/common.c | 5 ++--- arch/arm/plat-orion/include/plat/time.h | 4 ++-- arch/arm/plat-orion/time.c | 8 ++++---- 6 files changed, 14 insertions(+), 18 deletions(-) (limited to 'arch/arm/mach-orion5x') diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index ba55f631cccc..cb655998466d 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -185,7 +185,7 @@ void __init dove_i2c_init(void) ****************************************************************************/ void __init dove_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } static int get_tclk(void) @@ -196,8 +196,7 @@ static int get_tclk(void) static void __init dove_timer_init(void) { - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_DOVE_BRIDGE, get_tclk()); } diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index defceca51841..55bf9198caeb 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -514,7 +514,7 @@ void __init kirkwood_wdt_init(void) ****************************************************************************/ void __init kirkwood_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); /* * Some Kirkwood devices allocate their coherent buffers from atomic @@ -543,8 +543,7 @@ static void __init kirkwood_timer_init(void) { kirkwood_tclk = kirkwood_find_tclk(); - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); } diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index fcda4a4f830d..f123517a4bb8 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -338,13 +338,12 @@ void __init mv78xx0_uart3_init(void) ****************************************************************************/ void __init mv78xx0_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } static void mv78xx0_timer_init(void) { - orion_time_init((unsigned long) BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_MV78XX0_TIMER_1, get_tclk()); } diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 79f9ffb9a142..58b754ff701c 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -203,7 +203,7 @@ void __init orion5x_wdt_init(void) ****************************************************************************/ void __init orion5x_init_early(void) { - orion_time_set_base((unsigned long) TIMER_VIRT_BASE); + orion_time_set_base(TIMER_VIRT_BASE); } int orion5x_tclk; @@ -224,8 +224,7 @@ static void __init orion5x_timer_init(void) { orion5x_tclk = orion5x_find_tclk(); - orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE, - BRIDGE_INT_TIMER1_CLR, + orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, IRQ_ORION5X_BRIDGE, orion5x_tclk); } diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h index 4d5f1f6e18df..07527e417c62 100644 --- a/arch/arm/plat-orion/include/plat/time.h +++ b/arch/arm/plat-orion/include/plat/time.h @@ -11,9 +11,9 @@ #ifndef __PLAT_TIME_H #define __PLAT_TIME_H -void orion_time_set_base(u32 timer_base); +void orion_time_set_base(void __iomem *timer_base); -void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask, +void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk); diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 1ed8d1397fcf..0f4fa863dd55 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = { }; void __init -orion_time_set_base(u32 _timer_base) +orion_time_set_base(void __iomem *_timer_base) { - timer_base = (void __iomem *)_timer_base; + timer_base = _timer_base; } void __init -orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, +orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, unsigned int irq, unsigned int tclk) { u32 u; @@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, /* * Set SoC-specific data. */ - bridge_base = (void __iomem *)_bridge_base; + bridge_base = _bridge_base; bridge_timer1_clr_mask = _bridge_timer1_clr_mask; ticks_per_jiffy = (tclk + HZ/2) / HZ; -- cgit v1.2.3-55-g7522 From 9b7b7d8b024d3e44412abbbb0206ab8f60c459ad Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Tue, 11 Sep 2012 14:27:26 +0200 Subject: arm: plat-orion: use void __iomem pointers for addr-map functions The functions for address mapping management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files. Signed-off-by: Thomas Petazzoni Acked-by: Arnd Bergmann Tested-by: Andrew Lunn Signed-off-by: Jason Cooper --- arch/arm/mach-dove/addr-map.c | 2 +- arch/arm/mach-kirkwood/addr-map.c | 5 +++-- arch/arm/mach-mv78xx0/addr-map.c | 4 ++-- arch/arm/mach-orion5x/addr-map.c | 5 +++-- arch/arm/plat-orion/addr-map.c | 11 ++++------- arch/arm/plat-orion/include/plat/addr-map.h | 4 ++-- 6 files changed, 15 insertions(+), 16 deletions(-) (limited to 'arch/arm/mach-orion5x') diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c index b92c9c7d1d6e..2a06c0163418 100644 --- a/arch/arm/mach-dove/addr-map.c +++ b/arch/arm/mach-dove/addr-map.c @@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i) static struct __initdata orion_addr_map_cfg addr_map_cfg = { .num_wins = 8, .remappable_wins = 4, - .bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE, + .bridge_virt_base = BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 1b8c75c529dc..8f0d162a1e1d 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -41,7 +41,7 @@ static struct __initdata orion_addr_map_cfg addr_map_cfg = { .num_wins = 8, .remappable_wins = 4, - .bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE, + .bridge_virt_base = BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { @@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void) /* * Setup MBUS dram target info. */ - orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); + orion_setup_cpu_mbus_target(&addr_map_cfg, + (void __iomem *) DDR_WINDOW_CPU_BASE); } diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c index 3358f079bcd1..a51fc247e73b 100644 --- a/arch/arm/mach-mv78xx0/addr-map.c +++ b/arch/arm/mach-mv78xx0/addr-map.c @@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void) */ if (mv78xx0_core_index() == 0) orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU0_BASE); + (void __iomem *) DDR_WINDOW_CPU0_BASE); else orion_setup_cpu_mbus_target(&addr_map_cfg, - DDR_WINDOW_CPU1_BASE); + (void __iomem *) DDR_WINDOW_CPU1_BASE); } void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index d309f53b7a0c..b5efc0fd31cb 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c @@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg, static struct orion_addr_map_cfg addr_map_cfg __initdata = { .num_wins = 8, .cpu_win_can_remap = cpu_win_can_remap, - .bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE, + .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE, }; static const struct __initdata orion_addr_map_info addr_map_info[] = { @@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void) /* * Setup MBUS dram target info. */ - orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); + orion_setup_cpu_mbus_target(&addr_map_cfg, + (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE); } void __init orion5x_setup_dev_boot_win(u32 base, u32 size) diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c index 367ca89ac403..a7b8060c293a 100644 --- a/arch/arm/plat-orion/addr-map.c +++ b/arch/arm/plat-orion/addr-map.c @@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info); static void __init __iomem * orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) { - return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); + return cfg->bridge_virt_base + (win << 4); } /* @@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg, * Setup MBUS dram target info. */ void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const u32 ddr_window_cpu_base) + const void __iomem *ddr_window_cpu_base) { - void __iomem *addr; int i; int cs; orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; - addr = (void __iomem *)ddr_window_cpu_base; - for (i = 0, cs = 0; i < 4; i++) { - u32 base = readl(addr + DDR_BASE_CS_OFF(i)); - u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); + u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i)); + u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i)); /* * Chip select enabled? diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h index fd556f77562c..0a746fdfaf74 100644 --- a/arch/arm/plat-orion/include/plat/addr-map.h +++ b/arch/arm/plat-orion/include/plat/addr-map.h @@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info; struct orion_addr_map_cfg { const int num_wins; /* Total number of windows */ const int remappable_wins; - const u32 bridge_virt_base; + void __iomem * const bridge_virt_base; /* If NULL, the default cpu_win_can_remap will be used, using the value in remappable_wins */ @@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, const u8 attr, const int remap); void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, - const u32 ddr_window_cpu_base); + const void __iomem *ddr_window_cpu_base); #endif -- cgit v1.2.3-55-g7522