From 684f741446f7a3108b4c167faf20214c42b7eeac Mon Sep 17 00:00:00 2001 From: Zhiwu Song Date: Tue, 30 Aug 2011 19:20:34 -0700 Subject: ARM: CSR: add rtc i/o bridge interface for SiRFprimaII The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song Signed-off-by: Barry Song Reviewed-by: Jamie Iles Acked-by: Arnd Bergmann --- arch/arm/mach-prima2/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-prima2/Makefile') diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index 7af7fc05d565..f49d70b86854 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile @@ -3,5 +3,6 @@ obj-y += irq.o obj-y += clock.o obj-y += rstc.o obj-y += prima2.o +obj-y += rtciobrg.o obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_CACHE_L2X0) += l2x0.o -- cgit v1.2.3-55-g7522