From d9a3bfbd7e80ecf24d2322659d5c0542f9d95e78 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Oct 2011 15:08:56 +0900 Subject: ARM: S3C24XX: Add infrastructure to transmit armdiv to common code This is needed for making the armdiv clock common to S3C2443 and S3C2416/2450. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/plat-s3c24xx/s3c2443-clock.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 07a4c81587ac..3f2117b8c0d4 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -160,6 +160,10 @@ static struct clk clk_prediv = { }, }; +static unsigned int *armdiv; +static int nr_armdiv; +static int armdivmask; + /* usbhost * * usb host bus-clock, usually 48MHz to provide USB bus clock timing @@ -470,10 +474,16 @@ static struct clksrc_clk *clksrcs[] __initdata = { }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, - fdiv_fn get_fdiv) + fdiv_fn get_fdiv, + unsigned int *divs, int nr_divs, + int divmask) { int ptr; + armdiv = divs; + nr_armdiv = nr_divs; + armdivmask = divmask; + /* s3c2443 parents h and p clocks from prediv */ clk_h.parent = &clk_prediv; clk_p.parent = &clk_prediv; -- cgit v1.2.3-55-g7522 From aab08eebdf87d3e6eda5c81f119423af63f5aee1 Mon Sep 17 00:00:00 2001 From: Heiko St?bner Date: Fri, 14 Oct 2011 15:08:56 +0900 Subject: ARM: S3C2443: Move clk_arm and clk_armdiv to common code The system-layout of the armdiv and armclk is common to S3C2443/S3C2416/S3C2450 and only differs in the array of possible dividers. Therefore it is possible to reuse the clock definitions for all of these SoCs. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c2443/clock.c | 85 +--------------------------------- arch/arm/plat-s3c24xx/s3c2443-clock.c | 87 +++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 83 deletions(-) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 88edc55838a1..6fda4bf09cdd 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -61,10 +61,10 @@ * * this clock is sourced from msysclk and can have a number of * divider values applied to it to then be fed into armclk. + * The real clock definition is done in s3c2443-clock.c, + * only the armdiv divisor table must be defined here. */ -/* armdiv divisor table */ - static unsigned int armdiv[16] = { [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, @@ -83,85 +83,6 @@ static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; } -static unsigned long s3c2443_armclk_roundrate(struct clk *clk, - unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - unsigned long calc; - unsigned best = 256; /* bigger than any value */ - unsigned div; - int ptr; - - for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) { - div = armdiv[ptr]; - calc = parent / div; - if (calc <= rate && div < best) - best = div; - } - - return parent / best; -} - -static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) -{ - unsigned long parent = clk_get_rate(clk->parent); - unsigned long calc; - unsigned div; - unsigned best = 256; /* bigger than any value */ - int ptr; - int val = -1; - - for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) { - div = armdiv[ptr]; - calc = parent / div; - if (calc <= rate && div < best) { - best = div; - val = ptr; - } - } - - if (val >= 0) { - unsigned long clkcon0; - - clkcon0 = __raw_readl(S3C2443_CLKDIV0); - clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK; - clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; - __raw_writel(clkcon0, S3C2443_CLKDIV0); - } - - return (val == -1) ? -EINVAL : 0; -} - -static struct clk clk_armdiv = { - .name = "armdiv", - .parent = &clk_msysclk.clk, - .ops = &(struct clk_ops) { - .round_rate = s3c2443_armclk_roundrate, - .set_rate = s3c2443_armclk_setrate, - }, -}; - -/* armclk - * - * this is the clock fed into the ARM core itself, from armdiv or from hclk. - */ - -static struct clk *clk_arm_sources[] = { - [0] = &clk_armdiv, - [1] = &clk_h, -}; - -static struct clksrc_clk clk_arm = { - .clk = { - .name = "armclk", - }, - .sources = &(struct clksrc_sources) { - .sources = clk_arm_sources, - .nr_sources = ARRAY_SIZE(clk_arm_sources), - }, - .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, -}; - /* hsspi * * high-speed spi clock, sourced from esysclk @@ -260,14 +181,12 @@ static struct clk init_clocks[] = { /* clocks to add straight away */ static struct clksrc_clk *clksrcs[] __initdata = { - &clk_arm, &clk_hsspi, &clk_hsmmc_div, }; static struct clk *clks[] __initdata = { &clk_hsmmc, - &clk_armdiv, }; void __init_or_cpufreq s3c2443_setup_clocks(void) diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 3f2117b8c0d4..f9c5b0343cf3 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -160,10 +160,95 @@ static struct clk clk_prediv = { }, }; +/* armdiv + * + * this clock is sourced from msysclk and can have a number of + * divider values applied to it to then be fed into armclk. +*/ + static unsigned int *armdiv; static int nr_armdiv; static int armdivmask; +static unsigned long s3c2443_armclk_roundrate(struct clk *clk, + unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + unsigned long calc; + unsigned best = 256; /* bigger than any value */ + unsigned div; + int ptr; + + for (ptr = 0; ptr < nr_armdiv; ptr++) { + div = armdiv[ptr]; + calc = parent / div; + if (calc <= rate && div < best) + best = div; + } + + return parent / best; +} + +static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) +{ + unsigned long parent = clk_get_rate(clk->parent); + unsigned long calc; + unsigned div; + unsigned best = 256; /* bigger than any value */ + int ptr; + int val = -1; + + for (ptr = 0; ptr < nr_armdiv; ptr++) { + div = armdiv[ptr]; + calc = parent / div; + if (calc <= rate && div < best) { + best = div; + val = ptr; + } + } + + if (val >= 0) { + unsigned long clkcon0; + + clkcon0 = __raw_readl(S3C2443_CLKDIV0); + clkcon0 &= ~armdivmask; + clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT; + __raw_writel(clkcon0, S3C2443_CLKDIV0); + } + + return (val == -1) ? -EINVAL : 0; +} + +static struct clk clk_armdiv = { + .name = "armdiv", + .parent = &clk_msysclk.clk, + .ops = &(struct clk_ops) { + .round_rate = s3c2443_armclk_roundrate, + .set_rate = s3c2443_armclk_setrate, + }, +}; + +/* armclk + * + * this is the clock fed into the ARM core itself, from armdiv or from hclk. + */ + +static struct clk *clk_arm_sources[] = { + [0] = &clk_armdiv, + [1] = &clk_h, +}; + +static struct clksrc_clk clk_arm = { + .clk = { + .name = "armclk", + }, + .sources = &(struct clksrc_sources) { + .sources = clk_arm_sources, + .nr_sources = ARRAY_SIZE(clk_arm_sources), + }, + .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 }, +}; + /* usbhost * * usb host bus-clock, usually 48MHz to provide USB bus clock timing @@ -462,6 +547,7 @@ static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, &clk_usb_bus, + &clk_armdiv, }; static struct clksrc_clk *clksrcs[] __initdata = { @@ -471,6 +557,7 @@ static struct clksrc_clk *clksrcs[] __initdata = { &clk_epllref, &clk_esysclk, &clk_msysclk, + &clk_arm, }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, -- cgit v1.2.3-55-g7522 From 5f33bd76f5c4df45cd5b2e4132c6451dac8afee9 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Oct 2011 15:08:56 +0900 Subject: ARM: S3C2443: Add get_rate operation for clk_armdiv Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/plat-s3c24xx/s3c2443-clock.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index f9c5b0343cf3..fea3d5c0252e 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -189,6 +189,19 @@ static unsigned long s3c2443_armclk_roundrate(struct clk *clk, return parent / best; } +static unsigned long s3c2443_armclk_getrate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned long clkcon0; + int val; + + clkcon0 = __raw_readl(S3C2443_CLKDIV0); + clkcon0 &= armdivmask; + val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT; + + return rate / armdiv[val]; +} + static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) { unsigned long parent = clk_get_rate(clk->parent); @@ -224,6 +237,7 @@ static struct clk clk_armdiv = { .parent = &clk_msysclk.clk, .ops = &(struct clk_ops) { .round_rate = s3c2443_armclk_roundrate, + .get_rate = s3c2443_armclk_getrate, .set_rate = s3c2443_armclk_setrate, }, }; -- cgit v1.2.3-55-g7522 From f9f7c7503f7002deffe4cb8409ccada075a52522 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Oct 2011 15:08:56 +0900 Subject: ARM: S3C2443: handle unset armdiv values gracefully The armdiv array may contain unset divider values. Check the relevant value to prevent division by zero errors. Also check for set nr_armdiv and armdivmask before meddling with clkdiv0. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/plat-s3c24xx/s3c2443-clock.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index fea3d5c0252e..31f97f1bb363 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -179,11 +179,16 @@ static unsigned long s3c2443_armclk_roundrate(struct clk *clk, unsigned div; int ptr; + if (!nr_armdiv) + return -EINVAL; + for (ptr = 0; ptr < nr_armdiv; ptr++) { div = armdiv[ptr]; - calc = parent / div; - if (calc <= rate && div < best) - best = div; + if (div) { + calc = parent / div; + if (calc <= rate && div < best) + best = div; + } } return parent / best; @@ -195,6 +200,9 @@ static unsigned long s3c2443_armclk_getrate(struct clk *clk) unsigned long clkcon0; int val; + if (!nr_armdiv || !armdivmask) + return -EINVAL; + clkcon0 = __raw_readl(S3C2443_CLKDIV0); clkcon0 &= armdivmask; val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT; @@ -211,12 +219,17 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) int ptr; int val = -1; + if (!nr_armdiv || !armdivmask) + return -EINVAL; + for (ptr = 0; ptr < nr_armdiv; ptr++) { div = armdiv[ptr]; - calc = parent / div; - if (calc <= rate && div < best) { - best = div; - val = ptr; + if (div) { + calc = parent / div; + if (calc <= rate && div < best) { + best = div; + val = ptr; + } } } -- cgit v1.2.3-55-g7522 From 866a1c8c354e613c2bf378a1cd562756d4a32e75 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Oct 2011 15:08:57 +0900 Subject: ARM: S3C2443: Accommodate cpufreq frequency scheme in armdiv Cpufreq uses frequencies in kHz and not Hz, so set_rate and round_rate would be called with a frequency of 266666000 instead of 266666666 but the clock functions check for rates smaller or equal to the targetrate. As the armdiv does not support steps this small we can accommodate this by simply also setting the last 3 digits of the calculated rate to zero. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/plat-s3c24xx/s3c2443-clock.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 31f97f1bb363..40a87206400f 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -185,7 +185,8 @@ static unsigned long s3c2443_armclk_roundrate(struct clk *clk, for (ptr = 0; ptr < nr_armdiv; ptr++) { div = armdiv[ptr]; if (div) { - calc = parent / div; + /* cpufreq provides 266mhz as 266666000 not 266666666 */ + calc = (parent / div / 1000) * 1000; if (calc <= rate && div < best) best = div; } @@ -225,7 +226,8 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate) for (ptr = 0; ptr < nr_armdiv; ptr++) { div = armdiv[ptr]; if (div) { - calc = parent / div; + /* cpufreq provides 266mhz as 266666000 not 266666666 */ + calc = (parent / div / 1000) * 1000; if (calc <= rate && div < best) { best = div; val = ptr; -- cgit v1.2.3-55-g7522 From 33ccedfd1b79a7cf649b2991e95bae415c013240 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Oct 2011 15:08:57 +0900 Subject: ARM: S3C24XX: use clk_get_rate to init fclk in common_setup_clocks Previously the fclk rate was calculated by dividing the pll through the divider value of the armdiv. With a real armdiv clk in place it's possible to simply read its value, which does essentially the same. This change makes the whole fdiv_fn function pointers supplied to s3c2443_common_init_clocks and s3c2443_common_setup_clocks obsolete, so remove it too. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c2416/clock.c | 11 ++--------- arch/arm/mach-s3c2443/clock.c | 11 ++--------- arch/arm/plat-s3c24xx/s3c2443-clock.c | 8 +++----- arch/arm/plat-samsung/include/plat/s3c2443.h | 5 ++--- 4 files changed, 9 insertions(+), 26 deletions(-) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 7aa0cfa2f9bd..afbbe8bc21d1 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -133,16 +133,9 @@ static struct clk hsmmc0_clk = { .ctrlbit = S3C2416_HCLKCON_HSMMC0, }; -static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0) -{ - clkcon0 &= S3C2416_CLKDIV0_ARMDIV_MASK; - - return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; -} - void __init_or_cpufreq s3c2416_setup_clocks(void) { - s3c2443_common_setup_clocks(s3c2416_get_pll, s3c2416_fclk_div); + s3c2443_common_setup_clocks(s3c2416_get_pll); } @@ -166,7 +159,7 @@ void __init s3c2416_init_clocks(int xtal) clk_epll.parent = &clk_epllref.clk; - s3c2443_common_init_clocks(xtal, s3c2416_get_pll, s3c2416_fclk_div, + s3c2443_common_init_clocks(xtal, s3c2416_get_pll, armdiv, ARRAY_SIZE(armdiv), S3C2416_CLKDIV0_ARMDIV_MASK); diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 6fda4bf09cdd..b93cb96f57a5 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -76,13 +76,6 @@ static unsigned int armdiv[16] = { [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, }; -static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0) -{ - clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK; - - return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; -} - /* hsspi * * high-speed spi clock, sourced from esysclk @@ -191,7 +184,7 @@ static struct clk *clks[] __initdata = { void __init_or_cpufreq s3c2443_setup_clocks(void) { - s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div); + s3c2443_common_setup_clocks(s3c2443_get_mpll); } void __init s3c2443_init_clocks(int xtal) @@ -202,7 +195,7 @@ void __init s3c2443_init_clocks(int xtal) clk_epll.rate = s3c2443_get_epll(epllcon, xtal); clk_epll.parent = &clk_epllref.clk; - s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div, + s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, armdiv, ARRAY_SIZE(armdiv), S3C2443_CLKDIV0_ARMDIV_MASK); diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 40a87206400f..d3ebbeedf6d9 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -520,8 +520,7 @@ static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) /* EPLLCON compatible enough to get on/off information */ -void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, - fdiv_fn get_fdiv) +void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) { unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); @@ -541,7 +540,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll, pll = get_mpll(mpllcon, xtal); clk_msysclk.clk.rate = pll; - fclk = pll / get_fdiv(clkdiv0); + fclk = clk_get_rate(&clk_armdiv); hclk = s3c2443_prediv_getrate(&clk_prediv); hclk /= s3c2443_get_hdiv(clkdiv0); pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); @@ -590,7 +589,6 @@ static struct clksrc_clk *clksrcs[] __initdata = { }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, - fdiv_fn get_fdiv, unsigned int *divs, int nr_divs, int divmask) { @@ -620,5 +618,5 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c2443_common_setup_clocks(get_mpll, get_fdiv); + s3c2443_common_setup_clocks(get_mpll); } diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h index 5fc4ad0fd756..7fae1a050694 100644 --- a/arch/arm/plat-samsung/include/plat/s3c2443.h +++ b/arch/arm/plat-samsung/include/plat/s3c2443.h @@ -37,10 +37,9 @@ extern int s3c2443_baseclk_add(void); struct clk; /* some files don't need clk.h otherwise */ typedef unsigned int (*pll_fn)(unsigned int reg, unsigned int base); -typedef unsigned int (*fdiv_fn)(unsigned long clkcon0); -extern void s3c2443_common_setup_clocks(pll_fn get_mpll, fdiv_fn fdiv); -extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, fdiv_fn fdiv, +extern void s3c2443_common_setup_clocks(pll_fn get_mpll); +extern void s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, unsigned int *divs, int nr_divs, int divmask); -- cgit v1.2.3-55-g7522 From 5227a54a0f2c8ff4a0a971aac03511cf5545e1fb Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Oct 2011 15:35:08 +0900 Subject: ARM: S3C24XX: Add devname for hsmmc1 pclk S3C2443 uses hsmmc1 as its only hsmmc device and for S3C2416/S3C2450 it's the second hsmmc channel with the same PCLKCON bit. The hsmmc-if clocks on both systems already got a devname, as did the hsmmc pclk for hsmmc0 on the S3C2416. So to make it possible to identify the hsmmc1 pclk on S3C2416 add the correct devname for it. The sclk name on S3C2443 also is s3c-sdhci.1. Signed-off-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/plat-s3c24xx/s3c2443-clock.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/plat-s3c24xx') diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index d3ebbeedf6d9..5a21b15b2a97 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -426,6 +426,7 @@ static struct clk init_clocks[] = { .ctrlbit = S3C2443_HCLKCON_DMA5, }, { .name = "hsmmc", + .devname = "s3c-sdhci.1", .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2443_HCLKCON_HSMMC, -- cgit v1.2.3-55-g7522