From 45cc842d5b75ba8f9a958f2dd12b95c6dd0452bd Mon Sep 17 00:00:00 2001 From: Huazhong Tan Date: Thu, 18 Jan 2018 20:31:37 +0800 Subject: arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC Add cpld-syscon node to support the cpld control for hns-dsaf on the hip07 SoC. Signed-off-by: Huazhong Tan Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot/dts/hisilicon') diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2c01a21c3665..4bd6416122d5 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1127,6 +1127,12 @@ reg = <0x0 0xc0000000 0x0 0x10000>; }; + dsa_cpld: dsa_cpld@78000010 { + compatible = "syscon"; + reg = <0x0 0x78000010 0x0 0x100>; + reg-io-width = <2>; + }; + pcie_subctl: pcie_subctl@a0000000 { compatible = "hisilicon,pcie-sas-subctrl", "syscon"; reg = <0x0 0xa0000000 0x0 0x10000>; @@ -1258,6 +1264,7 @@ port@0 { reg = <0>; serdes-syscon = <&serdes_ctrl>; + cpld-syscon = <&dsa_cpld 0x0>; port-rst-offset = <0>; port-mode-offset = <0>; mc-mac-mask = [ff f0 00 00 00 00]; @@ -1267,6 +1274,7 @@ port@1 { reg = <1>; serdes-syscon= <&serdes_ctrl>; + cpld-syscon = <&dsa_cpld 0x4>; port-rst-offset = <1>; port-mode-offset = <1>; mc-mac-mask = [ff f0 00 00 00 00]; -- cgit v1.2.3-55-g7522 From 17f21343d7a0affc77b6cc1433cffa503433bbe6 Mon Sep 17 00:00:00 2001 From: Shameerali Kolothum Thodi Date: Thu, 14 Dec 2017 16:09:57 +0000 Subject: arm64: dts: hisi: Disable hisilicon smmu node on hip06/hip07 The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This makes it difficult for these platforms to have SMMU translation for MSI. In order to workaround this, ARM SMMUv3 driver requires a quirk to treat the MSI regions separately. Such a quirk is currently missing for DT based systems and therefore we need to explicitly disable the hip06/hip07 smmu entries in dts. Signed-off-by: Shameer Kolothum Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 56 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 25 ++++++++++++++ 2 files changed, 81 insertions(+) (limited to 'arch/arm64/boot/dts/hisilicon') diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a049b64f2101..35202ebe62a7 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -291,6 +291,13 @@ #interrupt-cells = <2>; num-pins = <128>; }; + + mbigen_pcie0: intc_pcie0 { + msi-parent = <&its_dsa 0x40085>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <10>; + }; }; mbigen_dsa@c0080000 { @@ -312,6 +319,31 @@ }; }; + /** + * HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -676,6 +708,30 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + pcie0: pcie@a0090000 { + compatible = "hisilicon,hip06-pcie-ecam"; + reg = <0 0xb0000000 0 0x2000000>, + <0 0xa0090000 0 0x10000>; + bus-range = <0 31>; + msi-map = <0x0000 &its_dsa 0x0000 0x2000>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 + 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 + 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 + 0x0 0 0 2 &mbigen_pcie0 650 4 + 0x0 0 0 3 &mbigen_pcie0 650 4 + 0x0 0 0 4 &mbigen_pcie0 650 4>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 4bd6416122d5..0600a6a84ab7 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1083,6 +1083,31 @@ }; }; + /** + * HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip07 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; -- cgit v1.2.3-55-g7522 From abd7d0972a192ee653efc7b151a6af69db58f2bb Mon Sep 17 00:00:00 2001 From: oscardagrach Date: Wed, 17 Jan 2018 14:35:30 -0600 Subject: arm64: dts: hikey: Enable HS200 mode on eMMC According to the hi6220 datasheet, the MMC controller is JEDEC eMMC 4.5 compliant, in addition to supporting a clock of up to 150MHz. The Hikey schematic also indicates the device utilizes 1.8v signaling. Define these parameters in the device tree to enable HS200 mode. Signed-off-by: Ryan Grachek Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64/boot/dts/hisilicon') diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index e94fa1a53192..94e74c056014 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -299,7 +299,9 @@ /* GPIO blocks 16 thru 19 do not appear to be routed to pins */ dwmmc_0: dwmmc0@f723d000 { + max-frequency = <150000000>; cap-mmc-highspeed; + mmc-hs200-1_8v; non-removable; bus-width = <0x8>; vmmc-supply = <&ldo19>; -- cgit v1.2.3-55-g7522 From 183879d8c6a6b4d8904330b21de4f27fb121179a Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 9 Feb 2018 14:28:05 +0530 Subject: ARM64: dts: hi6220: Remove "cooling-{min|max}-level" for CPU nodes The "cooling-min-level" and "cooling-max-level" properties are not parsed by any part of the kernel currently and the max cooling state of a CPU cooling device is found by referring to the cpufreq table instead. Moreover, the entries are incorrect here as min level is 4 and the max level is 0. Remove the unused properties from the CPU nodes. Signed-off-by: Viresh Kumar Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64/boot/dts/hisilicon') diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 6a180d1926e8..fca8e4ee98e7 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -88,8 +88,6 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - cooling-min-level = <4>; - cooling-max-level = <0>; #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; dynamic-power-coefficient = <311>; -- cgit v1.2.3-55-g7522 From 6bbec98e91e688bc7513508992a537d743cb61c3 Mon Sep 17 00:00:00 2001 From: Dmitry Shmidt Date: Thu, 1 Mar 2018 20:18:47 +0800 Subject: arm64: dts: hi6220: enable watchdog This patch is to add watchdog binding for Hi6220 on Hikey board. Signed-off-by: Dmitry Shmidt Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64/boot/dts/hisilicon') diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index fca8e4ee98e7..586b281cd531 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -815,6 +815,14 @@ pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; }; + watchdog0: watchdog@f8005000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xf8005000 0x0 0x1000>; + interrupts = ; + clocks = <&ao_ctrl HI6220_WDT0_PCLK>; + clock-names = "apb_pclk"; + }; + tsensor: tsensor@0,f7030700 { compatible = "hisilicon,tsensor"; reg = <0x0 0xf7030700 0x0 0x1000>; -- cgit v1.2.3-55-g7522 From 928c4a5ce8684d2c8a37543b3361cfc12d83b167 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Tue, 9 Jan 2018 12:32:42 +0800 Subject: arm64: dts: Hi3660: Remove 'CPU_NAP' idle state Thanks a lot for Vincent Guittot careful work to find bug for 'CPU_NAP' idle state. At early time, the CPU CA73 CPU_NAP idle state has been supported on Hikey960. Later we found the system has the hang issue and for resolving this issue Hisilicon released new MCU firmware, but unfortunately the new MCU firmware has side effect and results in the CA73 CPU cannot really enter CPU_NAP state and roll back to WFI state. After discussion we cannot see the possibility to enable CA73 CPU_NAP state anymore on Hikey960, based on this conclusion we should remove this state from DT binding. Cc: Daniel Lezcano Cc: Kevin Wang Cc: Vincent Guittot Signed-off-by: Leo Yan Tested-by: Vincent Guittot Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 32 ++++--------------------------- 1 file changed, 4 insertions(+), 28 deletions(-) (limited to 'arch/arm64/boot/dts/hisilicon') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 63d4f9dca77f..4ce4c282e19e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -100,11 +100,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = < - &CPU_NAP - &CPU_SLEEP - &CLUSTER_SLEEP_1 - >; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; }; @@ -114,11 +110,7 @@ reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = < - &CPU_NAP - &CPU_SLEEP - &CLUSTER_SLEEP_1 - >; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; }; @@ -128,11 +120,7 @@ reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = < - &CPU_NAP - &CPU_SLEEP - &CLUSTER_SLEEP_1 - >; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; }; @@ -142,25 +130,13 @@ reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&A73_L2>; - cpu-idle-states = < - &CPU_NAP - &CPU_SLEEP - &CLUSTER_SLEEP_1 - >; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>; capacity-dmips-mhz = <1024>; }; idle-states { entry-method = "psci"; - CPU_NAP: cpu-nap { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0000001>; - entry-latency-us = <7>; - exit-latency-us = <2>; - min-residency-us = <15>; - }; - CPU_SLEEP: cpu-sleep { compatible = "arm,idle-state"; local-timer-stop; -- cgit v1.2.3-55-g7522