From ba2b043e90f264df1969c4428bc89d7121e475e8 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Tue, 9 Jan 2018 09:42:21 +0800 Subject: arm64: dts: rockchip: Add cif test clocks for rk3399 There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by: Shunqian Zheng Reviewed-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 7aa2144e0d47..85b30c984acf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -2293,6 +2293,23 @@ }; }; + testclk { + test_clkout0: test-clkout0 { + rockchip,pins = + <0 0 RK_FUNC_1 &pcfg_pull_none>; + }; + + test_clkout1: test-clkout1 { + rockchip,pins = + <2 25 RK_FUNC_2 &pcfg_pull_none>; + }; + + test_clkout2: test-clkout2 { + rockchip,pins = + <0 8 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + tsadc { otp_gpio: otp-gpio { rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v1.2.3-55-g7522 From 2171f4fdac060e05826f9972a19bfdb569f5dcfe Mon Sep 17 00:00:00 2001 From: Levin Du Date: Tue, 23 Jan 2018 10:10:17 +0800 Subject: arm64: dts: rockchip: add roc-rk3328-cc board The roc-rk3328-cc is a credit card size single board computer using the Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting up to 2GB 2133MHz LPDDR4 memory. It provides eMMC module socket, MicroSD Card slot, USB 2.0/3.0, Gigabit Ethernet, HDMI/CVBS, Infrared Receiver, SPDIF/I2S, and SPI/I2C/UART/PWM interfaces. The devicetree currently supports basic peripherals. Signed-off-by: Levin Du Reviewed-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 267 +++++++++++++++++++++ 3 files changed, 272 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 326d24bca1a9..0f76a621015c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -50,6 +50,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; +- Firefly roc-rk3328-cc board: + Required root node properties: + - compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + - ChipSPARK PopMetal-RK3288 board: Required root node properties: - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index ce2701e37d00..cf14b8679eac 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts new file mode 100644 index 000000000000..246c317f6a68 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Firefly roc-rk3328-cc"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x25>; + rx_delay = <0x11>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- cgit v1.2.3-55-g7522 From 32c79915e081c82dce4e0ae8fc92d4169a829bff Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Tue, 30 Jan 2018 11:15:55 +0100 Subject: arm64: dts: rockchip: enable tsadc on rk3399-puma Enable the SoC thermal sensor on RK3399-Q7 (Puma). As we want to do do a full board reset instead of just a SoC one, set hw-tshut-mode to GPIO. Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 1fc5060d7027..ce15a57a5b85 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -505,6 +505,12 @@ }; }; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + &u2phy1 { status = "okay"; -- cgit v1.2.3-55-g7522 From 0efaf807839375b3a20366b8a057694c0ccad37b Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Sat, 3 Feb 2018 16:50:15 +0100 Subject: arm64: dts: rockchip: add i2s0-2ch-bus pins on rk3399 Add pin definition for I2S0 if used as a 2-channel only bus. Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 85b30c984acf..f689b1363f9c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -2043,6 +2043,16 @@ }; i2s0 { + i2s0_2ch_bus: i2s0-2ch-bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>, + <3 31 RK_FUNC_1 &pcfg_pull_none>, + <4 0 RK_FUNC_1 &pcfg_pull_none>; + }; + i2s0_8ch_bus: i2s0-8ch-bus { rockchip,pins = <3 24 RK_FUNC_1 &pcfg_pull_none>, -- cgit v1.2.3-55-g7522 From 2d3c2d56a3355d86a10fc74c82cc8753fb7f9eb5 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Tue, 13 Feb 2018 15:35:48 +0100 Subject: arm64: dts: rockchip: add cdn-dp node for rk3399. Add a node for the cdn DP controller which is embedded in the rk3399 SoC. Signed-off-by: Chris Zhong Signed-off-by: Enric Balletbo i Serra [fixed whitespaces instead of tabs, dropped unnecessary address+size-cells and fixed the number of interrupt cells] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index f689b1363f9c..65a42eee01de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -457,6 +457,42 @@ }; }; + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + assigned-clocks = <&cru SCLK_DP_CORE>; + assigned-clock-rates = <100000000>; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + power-domains = <&power RK3399_PD_HDCP>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; + gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -1547,6 +1583,11 @@ reg = <3>; remote-endpoint = <&mipi1_in_vopl>; }; + + vopl_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopl>; + }; }; }; @@ -1599,6 +1640,11 @@ reg = <3>; remote-endpoint = <&mipi1_in_vopb>; }; + + vopb_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopb>; + }; }; }; -- cgit v1.2.3-55-g7522 From 2490add2549bc46c6007600c01563cc9787ad59e Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Tue, 13 Feb 2018 15:35:49 +0100 Subject: arm64: dts: rockchip: enable DP for rk3399-gru Enable cdn_dp and create a cdn-dp-sound for the DP audio. Delete the endpoints between dp and vopL for gru, since we want the DP only use VOP big, which can support 4K mode. Signed-off-by: Chris Zhong Signed-off-by: Enric Balletbo i Serra [dropped vop-hacks] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 03f195025390..6e50768a34ce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -515,10 +515,15 @@ compatible = "rockchip,rk3399-gru-sound"; rockchip,cpu = <&i2s0 &i2s2>; rockchip,codec = <&max98357a &headsetcodec - &codec &wacky_spi_audio>; + &codec &wacky_spi_audio &cdn_dp>; }; }; +&cdn_dp { + status = "okay"; + extcon = <&usbc_extcon0>, <&usbc_extcon1>; +}; + /* * Set some suspend operating points to avoid OVP in suspend * -- cgit v1.2.3-55-g7522 From 1255fe0340592a44c666b64f9d5c3650cc69bb54 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Thu, 15 Feb 2018 13:46:50 +0000 Subject: arm64: dts: rockchip: Fix RK3328 UART DMAs Using a serial console on RK3328 provokes an error from of_dma_request_slave_channel() since the UART nodes have a "dmas" property but are missing the mandatory "dma-names" to go with it. Replace the bogus "#dma-cells" - these UARTs are DMA channel consumers, not providers - with the appropriate names instead. DMA still doesn't actually work, since the PL330 driver doesn't quite implement everything the 8250 driver demands, but at least it makes the DT correct. Signed-off-by: Robin Murphy Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index a037ee56fead..822488bdf364 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -318,7 +318,7 @@ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 2>, <&dmac 3>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; reg-io-width = <4>; @@ -333,7 +333,7 @@ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "sclk_uart", "pclk_uart"; dmas = <&dmac 4>, <&dmac 5>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; reg-io-width = <4>; @@ -348,7 +348,7 @@ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; dmas = <&dmac 6>, <&dmac 7>; - #dma-cells = <2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart2m1_xfer>; reg-io-width = <4>; -- cgit v1.2.3-55-g7522 From d99a02bcfa8152dd82f6be4da1816da4f52cf002 Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Tue, 30 Jan 2018 13:39:29 +0100 Subject: arm64: dts: rockchip: add RK3368-uQ7 (Lion) SoM The RK3368-uQ7 SoM is a uQseven-compatible (40mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3368. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit 1.8V interface) * SD card (on a baseboad) via edge connector * Gigabit Ethernet with on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI-DSI/LVDS * MIPI-CSI * USB - 1x USB 2.0 dual-role - 1x USB 2.0 host * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 317 ++++++++++++++++++++++++++ 1 file changed, 317 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi new file mode 100644 index 000000000000..1315972412df --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "rk3368.dtsi" + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + i2cmux1 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c1>; + mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + + /* Q7_GPO_I2C */ + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Q7_SMB */ + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2cmux2 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c2>; + mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + + /* Q7_LVDS_BLC_I2C */ + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + cooling-min-state = <0>; + cooling-max-state = <9>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; + }; + + /* Q7_GP2_I2C */ + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_module>; + + module_led1 { + label = "module_led1"; + gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + + module_led2 { + label = "module_led2"; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + clock-frequency = <150000000>; + disable-wp; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc33_io>; + vqmmc-supply = <&vcc18_io>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc33_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + tx_delay = <0x10>; + rx_delay = <0x10>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_sys>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: DCDC_REG2 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + }; + + vcc33_io: DCDC_REG4 { + regulator-name = "vcc33_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc33_video: LDO_REG2 { + regulator-name = "vcc33_video"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd10_pll: LDO_REG3 { + regulator-name = "vdd10_pll"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc18_io: LDO_REG4 { + regulator-name = "vcc18_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + vdd10_video: LDO_REG6 { + regulator-name = "vdd10_video"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc18_video: LDO_REG8 { + regulator-name = "vcc18_video"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&pinctrl { + leds { + led_pins_module: led-module-gpio { + rockchip,pins = + , + ; + }; + }; + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = ; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = ; + }; + }; +}; + +&spi1 { + status = "okay"; + + norflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; -- cgit v1.2.3-55-g7522 From 0aaf2359593f69f0ac4b5fc5e14fa2219698a0d5 Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Tue, 30 Jan 2018 13:39:30 +0100 Subject: arm64: dts: rockchip: add Haikou baseboard with RK3368-uQ7 SoM Haikou is a Qseven and μQseven baseboard used in Theobroma Systems evaluation kits. This dts adds a version for use with a RK3368-uQ7 SoM called Lion. Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3368-lion-haikou.dts | 146 +++++++++++++++++++++ 2 files changed, 147 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index cf14b8679eac..1e57f87f30c4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts new file mode 100644 index 000000000000..fca8e87d8f52 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "rk3368-lion.dtsi" + +/ { + model = "Theobroma Systems RK3368-uQ7 Baseboard"; + compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2cmux2 { + i2c@0 { + eeprom: eeprom@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + }; + }; + + leds { + pinctrl-0 = <&led_pins_module>, <&led_sd_haikou>; + + sd-card-led { + label = "sd_card_led"; + gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi2 { + cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart1 { + /* alternate function of GPIO5/6 */ + status = "disabled"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&haikou_pin_hog>; + + hog { + haikou_pin_hog: haikou-pin-hog { + rockchip,pins = + /* LID_BTN */ + , + /* BATLOW# */ + , + /* SLP_BTN# */ + , + /* BIOS_DISABLE# */ + ; + }; + }; + + leds { + led_sd_haikou: led-sd-gpio { + rockchip,pins = + ; + }; + }; + + sdmmc { + sdmmc_cd_gpio: sdmmc-cd-gpio { + rockchip,pins = + ; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + ; + }; + }; +}; -- cgit v1.2.3-55-g7522 From 51923db733659b9cf0f68f23ab89d5ab3027f761 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Sun, 18 Feb 2018 16:43:59 +0100 Subject: arm64: dts: rockchip: vdd_log on rk3399-sapphire is not an i2c slave The vdd_log power supply is controlled by a PWM pin, not by i2c register access. There is a boot message that reports an error about not being able to bring that supply up. Signed-off-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 0f873c897d0d..46c95ccfd5cb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -143,6 +143,17 @@ regulator-always-on; vin-supply = <&vcc_sys>; }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; }; &cpu_l0 { @@ -421,17 +432,6 @@ regulator-off-in-suspend; }; }; - - vdd_log: vdd-log { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - regulator-name = "vdd_log"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; - }; }; &i2c3 { -- cgit v1.2.3-55-g7522 From 139eabece9a66cb6ae694369cfa4c64badbf994a Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Mon, 19 Feb 2018 09:18:53 +0100 Subject: arm64: dts: rockchip: move i2s0 node from baseboard to SoM on rk3399-puma The I2S definition is part of the SoM and therefore should be in rk3399-puma.dtsi. Also correct the number of channels available. Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 8 -------- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 9a7486058455..8fd0d7ba1dc9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -117,14 +117,6 @@ clock-frequency = <400000>; }; -&i2s0 { - status = "okay"; - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; - #sound-dai-cells = <0>; - status = "okay"; -}; - &pcie_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index ce15a57a5b85..fc913e2d962f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -435,6 +435,14 @@ }; }; +&i2s0 { + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + status = "okay"; +}; + &io_domains { status = "okay"; bt656-supply = <&vcc_1v8>; -- cgit v1.2.3-55-g7522 From d95ed4308e2f5709193c612c4c06021afdb58975 Mon Sep 17 00:00:00 2001 From: Klaus Goger Date: Mon, 19 Feb 2018 09:18:54 +0100 Subject: arm64: dts: rockchip: enable I2S codec on rk3399-puma-haikou Enable the NXP SGTL5000 audio codec on the RK3399-Q7 EVK baseboard Haikou. Signed-off-by: Klaus Goger Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 63 ++++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 14 +++++ 2 files changed, 77 insertions(+) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 8fd0d7ba1dc9..7d3e8bfd51dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -61,6 +61,30 @@ }; }; + i2s0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + clocks = <&sgtl5000_clk>; + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + bitclock-master; + frame-master; + sound-dai = <&i2s0>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + dc_12v: dc-12v { compatible = "regulator-fixed"; regulator-name = "dc_12v"; @@ -80,6 +104,16 @@ vin-supply = <&dc_12v>; }; + vcc5v0_baseboard: vcc5v0-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + vcc5v0_otg: vcc5v0-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -89,6 +123,24 @@ regulator-name = "vcc5v0_otg"; regulator-always-on; }; + + vdda_codec: vdda-codec { + compatible = "regulator-fixed"; + regulator-name = "vdda_codec"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_baseboard>; + }; + + vddd_codec: vddd-codec { + compatible = "regulator-fixed"; + regulator-name = "vddd_codec"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_baseboard>; + }; }; &i2c1 { @@ -110,6 +162,17 @@ &i2c4 { status = "okay"; clock-frequency = <400000>; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vdda_codec>; + VDDIO-supply = <&vdda_codec>; + VDDD-supply = <&vddd_codec>; + status = "okay"; + }; }; &i2c6 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index fc913e2d962f..4a2d06abe9c1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -443,6 +443,20 @@ status = "okay"; }; +/* + * As Q7 does not specify neither a global nor a RX clock for I2S these + * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. + * Therefore we have to redefine the i2s0_2ch_bus definition to prevent + * conflicts. + */ +&i2s0_2ch_bus { + rockchip,pins = + , + , + , + ; +}; + &io_domains { status = "okay"; bt656-supply = <&vcc_1v8>; -- cgit v1.2.3-55-g7522 From 64ca41a8ff9dcc524e228e654f8bdf2dcd45c559 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 Feb 2018 08:59:37 +0100 Subject: arm64: dts: rockchip: move rk3399-sapphire sdio to excavator baseboard The sdio signals are routed through the connector to the baseboard, where the wifi module is also located. So move the sdio node to the excavator as well. Signed-off-by: Heiko Stuebner Tested-by: Vicente Bergas --- .../boot/dts/rockchip/rk3399-sapphire-excavator.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 16 ---------------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index b7bd88fb3ae3..68416fae4fea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -232,6 +232,22 @@ }; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + clock-frequency = <50000000>; + disable-wp; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &spdif { i2c-scl-rising-time-ns = <450>; i2c-scl-falling-time-ns = <15>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 46c95ccfd5cb..31568b4e8aa1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -520,22 +520,6 @@ status = "okay"; }; -&sdio0 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - clock-frequency = <50000000>; - disable-wp; - keep-power-in-suspend; - max-frequency = <50000000>; - mmc-pwrseq = <&sdio_pwrseq>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; - sd-uhs-sdr104; - status = "okay"; -}; - &sdmmc { bus-width = <4>; cap-mmc-highspeed; -- cgit v1.2.3-55-g7522 From 43798872d846a61d227b407209233b898c5497dc Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 20 Feb 2018 00:11:01 +0100 Subject: arm64: dts: rockchip: move rk3399-sapphire i2s2 to daughterboard The i2s2 drives the HDMI audio, which has the connector on the daughterboard. Signed-off-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 5 ----- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index 68416fae4fea..024038ef4f54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -207,11 +207,6 @@ status = "okay"; }; -&i2s2 { - #sound-dai-cells = <0>; - status = "okay"; -}; - &pinctrl { buttons { pwr_btn: pwr-btn { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 31568b4e8aa1..a4548e64d3a2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -440,6 +440,11 @@ status = "okay"; }; +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + &io_domains { status = "okay"; -- cgit v1.2.3-55-g7522 From 3811c91524368bc162806e042047b17949af631b Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 20 Feb 2018 00:11:02 +0100 Subject: arm64: dts: rockchip: move rk3399-sapphire pwr_btn to daughterboard The power button is located on the daughterboard. Signed-off-by: Vicente Bergas Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-sapphire-excavator.dts | 23 ---------------------- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 23 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index 024038ef4f54..56952d1a3fb8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -41,7 +41,6 @@ */ /dts-v1/; -#include #include "rk3399-sapphire.dtsi" / { @@ -95,22 +94,6 @@ }; }; - keys: gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - power { - debounce-interval = <100>; - gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; - label = "GPIO Power"; - linux,code = ; - linux,input-type = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_btn>; - wakeup-source; - }; - }; - rt5651-sound { compatible = "simple-audio-card"; simple-audio-card,name = "realtek,rt5651-codec"; @@ -208,12 +191,6 @@ }; &pinctrl { - buttons { - pwr_btn: pwr-btn { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index a4548e64d3a2..e5b0369e197f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -41,6 +41,7 @@ */ #include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -102,6 +103,22 @@ regulator-max-microvolt = <12000000>; }; + keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + linux,input-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_btn>; + wakeup-source; + }; + }; + /* switched by pmic_sleep */ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { compatible = "regulator-fixed"; @@ -475,6 +492,12 @@ }; &pinctrl { + buttons { + pwr_btn: pwr-btn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = -- cgit v1.2.3-55-g7522 From 0626d183479480c878c15157a38d6dd962c1dae6 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 19 Feb 2018 09:04:46 +0100 Subject: arm64: dts: rockchip: add a standalone version of the rk3399 sapphire While the sapphire board is a system-on-module and mostly used with the excavator baseboard, it is also possible to use it standalone without any base. So add a board-variant for this type. Signed-off-by: Heiko Stuebner Tested-by: Vicente Bergas Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 ++++ arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts | 12 ++++++++++++ 3 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 9a3e98356b1e..1c1d62d03c4f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -185,6 +185,10 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; +- Rockchip RK3399 Sapphire board standalone: + Required root node properties: + - compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; + - Rockchip RK3399 Sapphire Excavator board: Required root node properties: - compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1e57f87f30c4..48a83f882947 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -12,4 +12,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts new file mode 100644 index 000000000000..5a58060447cf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3399-sapphire.dtsi" + +/ { + model = "Sapphire-RK3399 Board"; + compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; +}; -- cgit v1.2.3-55-g7522 From 3f7f3b0fb4563947424673d9b6786f46111462d9 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Mon, 12 Mar 2018 09:50:48 +0800 Subject: arm64: dts: rockchip: assign clock rate for ACLK_VIO on rk3399 The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by: Shunqian Zheng Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 ++++-- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 6e50768a34ce..300f11daf1ae 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -586,7 +586,8 @@ <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>; assigned-clock-rates = <600000000>, <800000000>, <1000000000>, @@ -594,7 +595,8 @@ <37500000>, <100000000>, <100000000>, <50000000>, <800000000>, - <100000000>, <50000000>; + <100000000>, <50000000>, + <400000000>; }; &emmc_phy { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 65a42eee01de..a8340d94396e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1322,7 +1322,8 @@ <&cru PCLK_PERIHP>, <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, - <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>; assigned-clock-rates = <594000000>, <800000000>, <1000000000>, @@ -1330,7 +1331,8 @@ <37500000>, <100000000>, <100000000>, <50000000>, <600000000>, - <100000000>, <50000000>; + <100000000>, <50000000>, + <400000000>; }; grf: syscon@ff770000 { -- cgit v1.2.3-55-g7522 From 3783f1eb8a8db3747e753c4aa972124e1309db4e Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 6 Mar 2018 15:09:13 +0800 Subject: arm64: dts: rockchip: remove keep-power-in-suspend from sdhci of rk3399-sapphire sdhci for rk3399-sapphire works for eMMC but keep-power-in-suspend is an optional property for SDIO. Signed-off-by: Shawn Lin Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts/rockchip') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index e5b0369e197f..079a0a4820fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -541,7 +541,6 @@ &sdhci { bus-width = <8>; - keep-power-in-suspend; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; non-removable; -- cgit v1.2.3-55-g7522