From 8459c159f7de832eaf888398d2abf466c388dfa6 Mon Sep 17 00:00:00 2001 From: Dirk Opfer Date: Sun, 6 Nov 2005 14:27:52 +0000 Subject: [ARM] 3088/1: PXA: Add machine support for the Sharp SL-6000x series of PDAs Patch from Dirk Opfer This patch adds basic machine support for the Sharp SL-6000x (Tosa) PDAs. Signed-off-by: Dirk Opfer Signed-off-by: Richard Purdie Signed-off-by: Russell King --- arch/arm/mach-pxa/Kconfig | 9 ++- arch/arm/mach-pxa/Makefile | 1 + arch/arm/mach-pxa/tosa.c | 162 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-pxa/tosa.c (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 3e5f69bb5ac4..b380a438e68f 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -27,7 +27,8 @@ config PXA_SHARPSL Say Y here if you intend to run this kernel on a Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita), - SL-C3000 (Spitz) or SL-C3100 (Borzoi) handheld computer. + SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) + handheld computer. endchoice @@ -37,7 +38,7 @@ choice prompt "Select target Sharp Zaurus device range" config PXA_SHARPSL_25x - bool "Sharp PXA25x models (SL-5600 and SL-C7xx)" + bool "Sharp PXA25x models (SL-5600, SL-C7xx and SL-C6000x)" select PXA25x config PXA_SHARPSL_27x @@ -80,6 +81,10 @@ config MACH_BORZOI depends PXA_SHARPSL_27x select PXA_SHARP_Cxx00 +config MACH_TOSA + bool "Enable Sharp SL-6000x (Tosa) Support" + depends PXA_SHARPSL + config PXA25x bool help diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f609a0f232cb..8bc72d07cea8 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_PXA_IDP) += idp.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o ssp.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o ssp.o obj-$(CONFIG_MACH_POODLE) += poodle.o +obj-$(CONFIG_MACH_TOSA) += tosa.o # Support for blinky lights led-y := leds.o diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c new file mode 100644 index 000000000000..400609f8b6a8 --- /dev/null +++ b/arch/arm/mach-pxa/tosa.c @@ -0,0 +1,162 @@ +/* + * Support for Sharp SL-C6000x PDAs + * Model: (Tosa) + * + * Copyright (c) 2005 Dirk Opfer + * + * Based on code written by Sharp/Lineo for 2.4 kernels + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "generic.h" + + +/* + * SCOOP Device + */ +static struct resource tosa_scoop_resources[] = { + [0] = { + .start = TOSA_CF_PHYS, + .end = TOSA_CF_PHYS + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct scoop_config tosa_scoop_setup = { + .io_dir = TOSA_SCOOP_IO_DIR, + .io_out = TOSA_SCOOP_IO_OUT, + +}; + +struct platform_device tosascoop_device = { + .name = "sharp-scoop", + .id = 0, + .dev = { + .platform_data = &tosa_scoop_setup, + }, + .num_resources = ARRAY_SIZE(tosa_scoop_resources), + .resource = tosa_scoop_resources, +}; + + +/* + * SCOOP Device Jacket + */ +static struct resource tosa_scoop_jc_resources[] = { + [0] = { + .start = TOSA_SCOOP_PHYS + 0x40, + .end = TOSA_SCOOP_PHYS + 0xfff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct scoop_config tosa_scoop_jc_setup = { + .io_dir = TOSA_SCOOP_JC_IO_DIR, + .io_out = TOSA_SCOOP_JC_IO_OUT, +}; + +struct platform_device tosascoop_jc_device = { + .name = "sharp-scoop", + .id = 1, + .dev = { + .platform_data = &tosa_scoop_jc_setup, + .parent = &tosascoop_device.dev, + }, + .num_resources = ARRAY_SIZE(tosa_scoop_jc_resources), + .resource = tosa_scoop_jc_resources, +}; + +static struct scoop_pcmcia_dev tosa_pcmcia_scoop[] = { +{ + .dev = &tosascoop_device.dev, + .irq = TOSA_IRQ_GPIO_CF_IRQ, + .cd_irq = TOSA_IRQ_GPIO_CF_CD, + .cd_irq_str = "PCMCIA0 CD", +},{ + .dev = &tosascoop_jc_device.dev, + .irq = TOSA_IRQ_GPIO_JC_CF_IRQ, + .cd_irq = -1, +}, +}; + + +static struct platform_device *devices[] __initdata = { + &tosascoop_device, + &tosascoop_jc_device, +}; + +static void __init tosa_init(void) +{ + pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN); + pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN); + + /* setup sleep mode values */ + PWER = 0x00000002; + PFER = 0x00000000; + PRER = 0x00000002; + PGSR0 = 0x00000000; + PGSR1 = 0x00FF0002; + PGSR2 = 0x00014000; + PCFR |= PCFR_OPDE; + + // enable batt_fault + PMCR = 0x01; + + platform_add_devices(devices, ARRAY_SIZE(devices)); + + scoop_num = 2; + scoop_devs = &tosa_pcmcia_scoop[0]; +} + +static void __init fixup_tosa(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi) +{ + sharpsl_save_param(); + mi->nr_banks=1; + mi->bank[0].start = 0xa0000000; + mi->bank[0].node = 0; + mi->bank[0].size = (64*1024*1024); +} + +MACHINE_START(TOSA, "SHARP Tosa") + .phys_ram = 0xa0000000, + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .fixup = fixup_tosa, + .map_io = pxa_map_io, + .init_irq = pxa_init_irq, + .init_machine = tosa_init, + .timer = &pxa_timer, +MACHINE_END -- cgit v1.2.3-55-g7522 From 84613387cb60bc760a4588822cd61fb88e1d7fad Mon Sep 17 00:00:00 2001 From: Alessandro Zummo Date: Sun, 6 Nov 2005 14:34:12 +0000 Subject: [ARM] 3089/1: ixp4xx AHB/PCI endianness fix Patch from Alessandro Zummo This patch fixes AHB/PCI endianness problems when the processor is in little-endian mode. The patch configures the CSR register closely following the directives in [1], paragraph 4.1, page 19. According to the considerations in [1], page 11, while the AHB bus supports both endian modes, on the IXP4XX it always uses big-endian. The PCI bus is connected to the South AHB. A wrong setting in the CSR register will thus cause a malfunctional PCI bus. A schematic diagram of the bus interconnections on the IXP4XX can be found in [1], page 18. The patch has been verified to work on the NSLU2 in both LE and BE modes. The author is Peter Korsgaard. [1] Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor: Understanding Big Endian and Little Endian Modes http://www.intel.com/design/network/applnots/25423701.pdf Signed-off-by: Alessandro Zummo Signed-off-by: Deepak Saxena Signed-off-by: Russell King --- arch/arm/mach-ixp4xx/common-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 2b544363c078..9795da270e3a 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c @@ -427,7 +427,7 @@ void __init ixp4xx_pci_preinit(void) #ifdef __ARMEB__ *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; #else - *PCI_CSR = PCI_CSR_IC; + *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE; #endif pr_debug("DONE\n"); -- cgit v1.2.3-55-g7522 From 7240f1f183f085f6b7af44ec274b5b6123dfdead Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 6 Nov 2005 14:34:13 +0000 Subject: [ARM] 3114/1: use ixp2000_reg_wrb in ixp2000 uengine loader Patch from Lennert Buytenhek Make the uengine loader use ixp2000_reg_wrb in the right places. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ixp2000/uengine.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-ixp2000/uengine.c b/arch/arm/mach-ixp2000/uengine.c index 43e234349d4a..ec4e007a22ef 100644 --- a/arch/arm/mach-ixp2000/uengine.c +++ b/arch/arm/mach-ixp2000/uengine.c @@ -91,8 +91,8 @@ EXPORT_SYMBOL(ixp2000_uengine_csr_write); void ixp2000_uengine_reset(u32 uengine_mask) { - ixp2000_reg_write(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask); - ixp2000_reg_write(IXP2000_RESET1, 0); + ixp2000_reg_wrb(IXP2000_RESET1, uengine_mask & ixp2000_uengine_mask); + ixp2000_reg_wrb(IXP2000_RESET1, 0); } EXPORT_SYMBOL(ixp2000_uengine_reset); @@ -452,21 +452,20 @@ static int __init ixp2000_uengine_init(void) /* * Reset microengines. */ - ixp2000_reg_write(IXP2000_RESET1, ixp2000_uengine_mask); - ixp2000_reg_write(IXP2000_RESET1, 0); + ixp2000_uengine_reset(ixp2000_uengine_mask); /* * Synchronise timestamp counters across all microengines. */ value = ixp2000_reg_read(IXP2000_MISC_CONTROL); - ixp2000_reg_write(IXP2000_MISC_CONTROL, value & ~0x80); + ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value & ~0x80); for (uengine = 0; uengine < 32; uengine++) { if (ixp2000_uengine_mask & (1 << uengine)) { ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0); ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0); } } - ixp2000_reg_write(IXP2000_MISC_CONTROL, value | 0x80); + ixp2000_reg_wrb(IXP2000_MISC_CONTROL, value | 0x80); return 0; } -- cgit v1.2.3-55-g7522 From b7ec479553b8755dd95ee988a957cbf2aef351dc Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Sun, 6 Nov 2005 14:42:37 +0000 Subject: [ARM] 3115/1: small optimizations to exception vector entry code Patch from Nicolas Pitre Since we know the value of cpsr on entry, we can replace the bic+orr with a single eor. Also remove a possible result delay (at least on XScale). Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/kernel/entry-armv.S | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index be439cab92c6..a511ec5b11a3 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -785,7 +785,7 @@ __kuser_helper_end: * SP points to a minimal amount of processor-private memory, the address * of which is copied into r0 for the mode specific abort handler. */ - .macro vector_stub, name, correction=0 + .macro vector_stub, name, mode, correction=0 .align 5 vector_\name: @@ -805,15 +805,14 @@ vector_\name: @ Prepare for SVC32 mode. IRQs remain disabled. @ mrs r0, cpsr - bic r0, r0, #MODE_MASK - orr r0, r0, #SVC_MODE + eor r0, r0, #(\mode ^ SVC_MODE) msr spsr_cxsf, r0 @ @ the branch table must immediately follow this code @ - mov r0, sp and lr, lr, #0x0f + mov r0, sp ldr lr, [pc, lr, lsl #2] movs pc, lr @ branch to handler in SVC mode .endm @@ -823,7 +822,7 @@ __stubs_start: /* * Interrupt dispatcher */ - vector_stub irq, 4 + vector_stub irq, IRQ_MODE, 4 .long __irq_usr @ 0 (USR_26 / USR_32) .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) @@ -846,7 +845,7 @@ __stubs_start: * Data abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ - vector_stub dabt, 8 + vector_stub dabt, ABT_MODE, 8 .long __dabt_usr @ 0 (USR_26 / USR_32) .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) @@ -869,7 +868,7 @@ __stubs_start: * Prefetch abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ - vector_stub pabt, 4 + vector_stub pabt, ABT_MODE, 4 .long __pabt_usr @ 0 (USR_26 / USR_32) .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) @@ -892,7 +891,7 @@ __stubs_start: * Undef instr entry dispatcher * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC */ - vector_stub und + vector_stub und, UND_MODE .long __und_usr @ 0 (USR_26 / USR_32) .long __und_invalid @ 1 (FIQ_26 / FIQ_32) -- cgit v1.2.3-55-g7522 From 756c7b748926b0baec6d2a921c3711679282c8fd Mon Sep 17 00:00:00 2001 From: Richard Purdie Date: Sun, 6 Nov 2005 15:03:23 +0000 Subject: [ARM] 3113/1: PXA: Allow machines to override (and also reuse) pxa pm functions Patch from Richard Purdie Update the PXA pm.c file to allow machines (such as the Sharp Zaurus) to override the standard pm functions but reuse/wrap them where needed. The init call is made slightly earlier to give machine code an init level to override them in removing any race. Signed-off-by: Richard Purdie Signed-off-by: Russell King --- arch/arm/mach-pxa/pm.c | 16 ++++++++++++---- include/asm-arm/arch-pxa/pm.h | 12 ++++++++++++ 2 files changed, 24 insertions(+), 4 deletions(-) create mode 100644 include/asm-arm/arch-pxa/pm.h (limited to 'arch/arm') diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index ac4dd4336160..f74b9af112dc 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c @@ -12,6 +12,7 @@ */ #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -72,7 +74,7 @@ enum { SLEEP_SAVE_START = 0, }; -static int pxa_pm_enter(suspend_state_t state) +int pxa_pm_enter(suspend_state_t state) { unsigned long sleep_save[SLEEP_SAVE_SIZE]; unsigned long checksum = 0; @@ -191,6 +193,8 @@ static int pxa_pm_enter(suspend_state_t state) return 0; } +EXPORT_SYMBOL_GPL(pxa_pm_enter); + unsigned long sleep_phys_sp(void *sp) { return virt_to_phys(sp); @@ -199,21 +203,25 @@ unsigned long sleep_phys_sp(void *sp) /* * Called after processes are frozen, but before we shut down devices. */ -static int pxa_pm_prepare(suspend_state_t state) +int pxa_pm_prepare(suspend_state_t state) { extern int pxa_cpu_pm_prepare(suspend_state_t state); return pxa_cpu_pm_prepare(state); } +EXPORT_SYMBOL_GPL(pxa_pm_prepare); + /* * Called after devices are re-setup, but before processes are thawed. */ -static int pxa_pm_finish(suspend_state_t state) +int pxa_pm_finish(suspend_state_t state) { return 0; } +EXPORT_SYMBOL_GPL(pxa_pm_finish); + /* * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. */ @@ -230,4 +238,4 @@ static int __init pxa_pm_init(void) return 0; } -late_initcall(pxa_pm_init); +device_initcall(pxa_pm_init); diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h new file mode 100644 index 000000000000..7a8a1cdf430d --- /dev/null +++ b/include/asm-arm/arch-pxa/pm.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2005 Richard Purdie + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +extern int pxa_pm_prepare(suspend_state_t state); +extern int pxa_pm_enter(suspend_state_t state); +extern int pxa_pm_finish(suspend_state_t state); -- cgit v1.2.3-55-g7522 From 4299051ebe89ab1eeadeaf4cf06ce63421412232 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 6 Nov 2005 15:46:57 +0000 Subject: [ARM] Fix missing declaration of cache_is_vivt() Signed-off-by: Russell King --- arch/arm/kernel/ecard.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index dceb826bd216..c445b0a848b2 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -41,6 +41,7 @@ #include #include +#include #include #include #include -- cgit v1.2.3-55-g7522 From 4fe15ba08fdb280536bd7019e8505969c4ac6852 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 6 Nov 2005 19:47:04 +0000 Subject: [ARM] Fix second missing declaration of cache_is_vivt() Signed-off-by: Russell King --- arch/arm/kernel/ecard.c | 1 - include/asm-arm/mmu_context.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index c445b0a848b2..dceb826bd216 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c @@ -41,7 +41,6 @@ #include #include -#include #include #include #include diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 57b8def83d41..3d4b810d8c38 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -13,6 +13,7 @@ #ifndef __ASM_ARM_MMU_CONTEXT_H #define __ASM_ARM_MMU_CONTEXT_H +#include #include #if __LINUX_ARM_ARCH__ >= 6 -- cgit v1.2.3-55-g7522 From 32f8b97ca39421057d8adef05b7219127355d60c Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 6 Nov 2005 19:49:21 +0000 Subject: [ARM] Don't call dump_cpu_info unless we're booting We don't want to call dump_cpu_info() from cpu_init() after boot since it produces a lot of unnecessary noise - since cpu_init() gets called on resume and hotplug cpu insertion events. Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c9b69771f92e..a6d7fb81330e 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -338,7 +338,8 @@ void cpu_init(void) BUG(); } - dump_cpu_info(cpu); + if (system_state == SYSTEM_BOOTING) + dump_cpu_info(cpu); /* * setup stacks for re-entrant exception handlers -- cgit v1.2.3-55-g7522 From 1555972231f3202f00e04f7c42d2db858e11b874 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sun, 6 Nov 2005 21:41:08 +0000 Subject: [ARM] Fix /proc/cpuinfo format for ARM SMP glibc expects to count lines beginning with "processor" to determine the number of processors, not lines beginning with "Processor". So, give glibc the format it expects. Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index a6d7fb81330e..85774165e9fd 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -839,7 +839,12 @@ static int c_show(struct seq_file *m, void *v) #if defined(CONFIG_SMP) for_each_online_cpu(i) { - seq_printf(m, "Processor\t: %d\n", i); + /* + * glibc reads /proc/cpuinfo to determine the number of + * online processors, looking for lines beginning with + * "processor". Give glibc what it expects. + */ + seq_printf(m, "processor\t: %d\n", i); seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n", per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ), (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100); -- cgit v1.2.3-55-g7522