From 94a038c2e6228727ae0549af75e97b9b634cd468 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 27 Oct 2010 10:06:32 -0400 Subject: Blackfin: bf561: update a few more SIC_SYSCR locations Looks like I missed a few new spots when renaming the SICA macros. Signed-off-by: Mike Frysinger --- arch/blackfin/mach-bf561/include/mach/pll.h | 24 ++++++++++++------------ arch/blackfin/mach-bf561/smp.c | 4 ++-- 2 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/blackfin/mach-bf561') diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h index f2b1fbdb8e72..5cdb655c4465 100644 --- a/arch/blackfin/mach-bf561/include/mach/pll.h +++ b/arch/blackfin/mach-bf561/include/mach/pll.h @@ -20,18 +20,18 @@ static __inline__ void bfin_write_PLL_CTL(unsigned int val) flags = hard_local_irq_save(); /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); bfin_write16(PLL_CTL, val); SSYNC(); asm("IDLE;"); - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); hard_local_irq_restore(flags); } @@ -45,18 +45,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val) flags = hard_local_irq_save(); /* Enable the PLL Wakeup bit in SIC IWR */ - iwr0 = bfin_read32(SICA_IWR0); - iwr1 = bfin_read32(SICA_IWR1); + iwr0 = bfin_read32(SIC_IWR0); + iwr1 = bfin_read32(SIC_IWR1); /* Only allow PPL Wakeup) */ - bfin_write32(SICA_IWR0, IWR_ENABLE(0)); - bfin_write32(SICA_IWR1, 0); + bfin_write32(SIC_IWR0, IWR_ENABLE(0)); + bfin_write32(SIC_IWR1, 0); bfin_write16(VR_CTL, val); SSYNC(); asm("IDLE;"); - bfin_write32(SICA_IWR0, iwr0); - bfin_write32(SICA_IWR1, iwr1); + bfin_write32(SIC_IWR0, iwr0); + bfin_write32(SIC_IWR1, iwr1); hard_local_irq_restore(flags); } diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index f540ed1257d6..be6083a7e42f 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle spin_lock(&boot_lock); - if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { + if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { /* CoreB already running, sending ipi to wakeup it */ platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); } else { /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ - bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); + bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); SSYNC(); } -- cgit v1.2.3-55-g7522