From a12cf0a8c6e2763ac865aa31f296557e07432b8a Mon Sep 17 00:00:00 2001
From: Greg Ungerer
Date: Tue, 9 Nov 2010 10:12:29 +1000
Subject: m68knommu: create bit definitions for the version 2 ColdFire cache
 controller

The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
 arch/m68k/include/asm/m5249sim.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'arch/m68k/include/asm/m5249sim.h')

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 21d0bbfbc0c9..4908b118f2fd 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -14,6 +14,8 @@
 #define	CPU_NAME		"COLDFIRE(m5249)"
 #define	CPU_INSTR_PER_JIFFY	3
 
+#include <asm/m52xxacr.h>
+
 /*
  *	Define the 5249 SIM register set addresses.
  */
-- 
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