From a5770df09541f88021390375f324b25124675355 Mon Sep 17 00:00:00 2001 From: Steven J. Hill Date: Thu, 19 Feb 2015 10:18:52 -0600 Subject: MIPS: Add set/clear CP0 macros for PageGrain register Build set and clear macros for the PageGrain register. Signed-off-by: Steven J. Hill Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9289/ Signed-off-by: Ralf Baechle --- arch/mips/mm/tlb-r4k.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/mm') diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index e90b2e899291..b2afa49beab0 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -485,11 +485,11 @@ static void r4k_tlb_configure(void) * Enable the no read, no exec bits, and enable large virtual * address. */ - u32 pg = PG_RIE | PG_XIE; #ifdef CONFIG_64BIT - pg |= PG_ELPA; + set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA); +#else + set_c0_pagegrain(PG_RIE | PG_XIE); #endif - write_c0_pagegrain(pg); } temp_tlb_entry = current_cpu_data.tlbsize - 1; -- cgit v1.2.3-55-g7522