From bd5050e38aec3055ff4257ade987d808ac93b582 Mon Sep 17 00:00:00 2001 From: Aneesh Kumar K.V Date: Tue, 29 May 2018 19:58:41 +0530 Subject: powerpc/mm/radix: Change pte relax sequence to handle nest MMU hang When relaxing access (read -> read_write update), pte needs to be marked invalid to handle a nest MMU bug. We also need to do a tlb flush after the pte is marked invalid before updating the pte with new access bits. We also move tlb flush to platform specific __ptep_set_access_flags. This will help us to gerid of unnecessary tlb flush on BOOK3S 64 later. We don't do that in this patch. This also helps in avoiding multiple tlbies with coprocessor attached. Signed-off-by: Aneesh Kumar K.V Signed-off-by: Michael Ellerman --- arch/powerpc/mm/pgtable-book3s64.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/powerpc/mm/pgtable-book3s64.c') diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c index 4a8150481a88..82fed87289de 100644 --- a/arch/powerpc/mm/pgtable-book3s64.c +++ b/arch/powerpc/mm/pgtable-book3s64.c @@ -52,7 +52,6 @@ int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address, */ __ptep_set_access_flags(vma, pmdp_ptep(pmdp), pmd_pte(entry), address, MMU_PAGE_2M); - flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE); } return changed; } -- cgit v1.2.3-55-g7522