From 44387e9ff25267c78a99229aca55ed750e9174c7 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Mon, 17 Mar 2008 15:27:09 +1100 Subject: [POWERPC] Fix PMU + soft interrupt disable bug Since the PMU is an NMI now, it can come at any time we are only soft disabled. We must hard disable around the two places we allow the kernel stack SLB and r1 to go out of sync. Otherwise the PMU exception can force a kernel stack SLB into another slot, which can lead to it getting evicted, which can lead to a nasty unrecoverable SLB miss in the exception entry code. Signed-off-by: Anton Blanchard Acked-by: Benjamin Herrenschmidt Acked-by: Olof Johansson Signed-off-by: Paul Mackerras --- arch/powerpc/mm/slb.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/powerpc/mm/slb.c') diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c index 47b06bad24ad..906daeda59a8 100644 --- a/arch/powerpc/mm/slb.c +++ b/arch/powerpc/mm/slb.c @@ -124,6 +124,12 @@ void slb_flush_and_rebolt(void) ksp_vsid_data = get_slb_shadow()->save_area[2].vsid; } + /* + * We can't take a PMU exception in the following code, so hard + * disable interrupts. + */ + hard_irq_disable(); + /* We need to do this all in asm, so we're sure we don't touch * the stack between the slbia and rebolting it. */ asm volatile("isync\n" -- cgit v1.2.3-55-g7522