From c6673cb54d191dd42935a61fcb0c452a4753fb23 Mon Sep 17 00:00:00 2001 From: FUJITA Tomonori Date: Wed, 30 Jun 2010 11:10:08 +0900 Subject: tile: set ARCH_KMALLOC_MINALIGN Architectures that handle DMA-non-coherent memory need to set ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe: the buffer doesn't share a cache with the others. Signed-off-by: FUJITA Tomonori Acked-by: Chris Metcalf --- arch/tile/include/asm/cache.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/tile') diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index ee597147e5cd..869a14f4ceae 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -31,6 +31,14 @@ #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) +/* + * TILE-Gx is fully coherents so we don't need to define + * ARCH_KMALLOC_MINALIGN. + */ +#ifndef __tilegx__ +#define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES +#endif + /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT #define SMP_CACHE_BYTES L2_CACHE_BYTES -- cgit v1.2.3-55-g7522