From f7face03c66cea12159191ba8d2a9ee735da0b0d Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Thu, 2 Jul 2009 23:23:30 +0800 Subject: MIPS: Loongson: PCI: Clean up pcimap setup Fixup the wrong original comment of pcimap, and make the source code more understandable. and also, some new extra consideration is added in. Signed-off-by: Wu Zhangjin Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-lemote/loongson.h | 17 ++++++++++++ arch/mips/include/asm/mach-lemote/pci.h | 4 +-- arch/mips/lemote/lm2e/pci.c | 41 ++++++++++++++++++---------- 3 files changed, 45 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/mips/include/asm/mach-lemote/loongson.h b/arch/mips/include/asm/mach-lemote/loongson.h index 76cc2bddfa43..916eacec94ec 100644 --- a/arch/mips/include/asm/mach-lemote/loongson.h +++ b/arch/mips/include/asm/mach-lemote/loongson.h @@ -33,4 +33,21 @@ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); extern void __init prom_init_env(void); +/* PCI Configuration Registers */ +#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) + +/* PCI_Hit*_Sel_* */ + +#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) +#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) +#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) +#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) +#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) +#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) + +/* PXArb Config & Status */ + +#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) +#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) + #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h index 92b2f59d890f..3e6b1300afb6 100644 --- a/arch/mips/include/asm/mach-lemote/pci.h +++ b/arch/mips/include/asm/mach-lemote/pci.h @@ -24,8 +24,8 @@ extern struct pci_ops bonito64_pci_ops; -#define LOONGSON2E_PCI_MEM_START 0x14000000UL -#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL +#define LOONGSON2E_PCI_MEM_START BONITO_PCILO1_BASE +#define LOONGSON2E_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) #define LOONGSON2E_PCI_IO_START 0x00004000UL #endif /* !__ASM_MACH_LEMOTE_PCI_H_ */ diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c index bee846e6d8a8..9812c30cc6eb 100644 --- a/arch/mips/lemote/lm2e/pci.c +++ b/arch/mips/lemote/lm2e/pci.c @@ -34,33 +34,44 @@ static struct pci_controller loongson2e_pci_controller = { .io_offset = 0x00000000UL, }; -static void __init ict_pcimap(void) +static void __init setup_pcimap(void) { /* - * local to PCI mapping: [256M,512M] -> [256M,512M]; differ from PMON - * + * local to PCI mapping for CPU accessing PCI space * CPU address space [256M,448M] is window for accessing pci space - * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] - * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 + * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] + * + * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 + * [<2G] [384M,448M] [320M,384M] [0M,64M] */ - /* 1,00 0110 ,0001 01,00 0000 */ - BONITO_PCIMAP = 0x46140; - - /* 1, 00 0010, 0000,01, 00 0000 */ - /* BONITO_PCIMAP = 0x42040; */ + BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | + BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | + BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | + BONITO_PCIMAP_WIN(0, 0); /* - * PCI to local mapping: [2G,2G+256M] -> [0,256M] + * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] */ - BONITO_PCIBASE0 = 0x80000000; - BONITO_PCIBASE1 = 0x00800000; - BONITO_PCIBASE2 = 0x90000000; + BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + /* size: 256M, burst transmission, pre-fetch enable, 64bit */ + LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; + LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; + LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; + LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; + + /* avoid deadlock of PCI reading/writing lock operation */ + LOONGSON_PCI_ISR4C = 0xd2000001ul; + /* can not change gnt to break pci transfer when device's gnt not + deassert for some broken device */ + LOONGSON_PXARB_CFG = 0x00fe0105ul; } static int __init pcibios_init(void) { - ict_pcimap(); + setup_pcimap(); loongson2e_pci_controller.io_map_base = mips_io_port_base; -- cgit v1.2.3-55-g7522