From eec26555ae9bf69da8bfe90cacdbc85d7a23391b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 27 May 2019 04:51:54 -0700 Subject: bus: ti-sysc: Enable interconnect target module autoidle bit on enable For interconnect target modules with autoidle bit wired, we need to manage it for enable and disable. Tested-by: Keerthy Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers/bus') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 412973829adc..46a8eb469cb2 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -893,7 +893,7 @@ set_midle: /* Set MIDLE mode */ idlemodes = ddata->cfg.midlemodes; if (!idlemodes || regbits->midle_shift < 0) - return 0; + goto set_autoidle; best_mode = fls(ddata->cfg.midlemodes) - 1; if (best_mode > SYSC_IDLE_MASK) { @@ -905,6 +905,14 @@ set_midle: reg |= best_mode << regbits->midle_shift; sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); +set_autoidle: + /* Autoidle bit must enabled separately if available */ + if (regbits->autoidle_shift >= 0 && + ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { + reg |= 1 << regbits->autoidle_shift; + sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); + } + return 0; } @@ -966,6 +974,9 @@ set_sidle: reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); reg |= best_mode << regbits->sidle_shift; + if (regbits->autoidle_shift >= 0 && + ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) + reg |= 1 << regbits->autoidle_shift; sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); return 0; -- cgit v1.2.3-55-g7522